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Choose the best IC integration method when designing a 3G handset
iPs and SoCs are currently in vogue. Understand whether they're right for your design.By Bill Krenik, Dennis Buss, and Peter Rickert, Texas Instruments
| CommsDesign
May 24, 2005 | | | |
The era of the voice-only mobile phone is behind us. While voice willalways be a key driver for mobile phone use, today's 3G handsets aremultimedia systems with color displays, games, audio, video, cameras,Bluetooth, GPS, WLAN, high-speed wide-area data services, and otheradvanced features. With so much functionality, the latest 3G phonesboost processing complexity by 5X to 10X over voice-only 2G phones. Inaddition, applications processing requirements jump even more.
Consumers expect allthese new features in sleek, ergonomic, reasonably priced handsets withbattery life at least equal to what they've become accustomed in lessfunctional handsets. Studies show that users won't accept handsets withtalk time below two hours. And they anticipate ever smaller physicaldevices that will somehow provide larger displays.
These apparentlycontradictory requirements—more complex features using less power andspace—place considerable pressure on component providers toaggressively integrate the electronics. System-in-package (SiP) andSystem-on-chip (SoC) are two approaches that help satisfy theseintegration demands. SoC, with its ability to reduce board real-estaterequirements, cut system costs, and lower power consumption, has beenembraced by phone makers and their semiconductor suppliers. SiP,capable of marrying semiconductors made with different processtechnologies in one package, is coming into its own in handsets. Eachapproach offers advantages and drawbacks.
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Mobile phone processorsrequire significant amounts of RAM to keep the processor cores runningwith minimal wait states. This means that on-chip level one (L1) andlevel two (L2) cache memory arrays must be large enough to keep theprocessor core pipelines loaded and prevent excessive off-chip fetches.
To get an understandingfor the amount of memory required in SoC applications, feature-laden2.5G handsets may have up to 16 Mbytes of NOR flash memory, and thesame amounts of NAND flash and DRAM. Sizes such as these are unsuitablefor an embedded solution because of the area required to implement themand the resulting negative impact on board space and cost.
The key to decidingwhether these memories should be embedded or off-chip is determiningwhether the embedded solution delivers more value than integrating theexternal memory. This means that any embedded solution should leveragethe integration from an architectural perspective. One exampleapplication is graphics, which requires high memory bandwidth. For thisrequirement, it's advantageous to use a wide memory bus to deliver theadded bandwidth. Bus width in these applications can be 256 or 512 bitswide. This wide bus-width is impractical with external memory. As aresult, the embedded solution delivers value beyond a cost reduction.
However, SoC integrationisn't cost-effective if the process complexity of the integrated chipis substantially higher than that of the isolated ICs. Consider theexample of a 50-mm2 logic chip and a 50-mm2 DRAMchip. Assume that both the 6LM logic chip and the 3LM DRAM chip eachrequire 26 mask levels. Using mask levels as a proxy for cost, the"cost" of the individual chips is 100 mm2 × 26 masks = 2600 mask-mm2. Now, if the logic and DRAM are integrated, the mask count increases to 32, and the "cost" rises to 3200 mask-mm2, a 23% increase! For most system designs, this increase would not be acceptable.
Another issue that ariseswith SoC memory integration is the fact that embedding a given processtechnology typically entails nine to twelve months of developmentbeyond the standard CMOS version of that same process technology node.This means that complex embedded memory solutions become availablealmost a year after the standard CMOS implementation.
SiP offers onecost-effective solution to the embedded memory dilemma. The stacked dieSiP implementation provides the same small footprint as a SoC solution.In this implementation one (or more) commodity memory die is stacked ontop of the SoC logic device. Low-cost wirebond assembly technologyinterconnects the devices, which are encapsulated in an inexpensivechip-sized ball-grid array (BGA) package (Fig. 1).
1. This photomicrograph of a stack die SiP shows the wire-bonding.Because the stacked dieapproach doesn't add process complexity to the high-performance CMOScommunications processor, but leverages cost-effective commoditymemory, it offers the best of both worlds. It doesn't normally requirecustom chips, which helps reduce time to market. And, because it addsspace vertically, rather than horizontally, it fits the footprintsuitable for battery-operated consumer products.
Analog and power-management integration
Today,analog and power management functions are normally implemented inanalog process technologies, very different from the deep submicronCMOS used for digital baseband chips. If the analog andpower-management functions can be implemented in deep submicron digitalCMOS without adding process complexity, then the SoC integration ofanalog and power management functions can be a low-cost approach.
The biggest challenge inimplementing high-speed and high-precision analog functions in digitalCMOS is the process' low power supply voltage. Other limitationsinclude poor matching of small components, high 1/f noise, and theabsence of on-chip passive components (resistors, capacitors, andvaractors) with adequate analog characteristics. Because of theselimitations, it usually isn't feasible to copy existing analogfunctions in digital CMOS. Instead, the total system must bere-optimized to take advantage of digital CMOS and to develop newarchitectures to exploit the benefits of low-voltage and low-costdigital logic. In most cases, these architectures are well-known, butthe low-voltage trade-offs are different:
- At low voltage, the power dissipated by flash converters is greatly reduced, thereby making flash architectures advantageous.
- Because flash converters have low power, multi-bit sigma-delta converters have advantages over single-bit architectures.
- Very fast logic allows offset compensation in a fraction of a sample period and enables small, low-power comparators.
- Oversampling DACs and ADCs become increasingly feasible at lowvoltage, thereby reducing kT/C noise and easing analog filterrequirements.
- Digital, self-calibration and dynamic element matching have increasing advantages at small feature size and low voltage.
In an example of are-optimized design, the 12-bit delta- sigma ADC takes advantage of thelogic and high-speed switching capability of 90nm CMOS. Such aconverter's high resolution and sampling rate allow more of theradio-channel signal processing to be done in the digital domain. Thisdigital processing improves flexibility and reduces cost and powerversus a more heavily analog implementation.
Power management isbecoming increasingly distributed, especially in low-powerapplications, because of the need to reduce standby power by puttingunused logic and memory in a standby or sleep mode. Much of this powermanagement functionality can be accomplished using switches to activateor deactivate logic blocks. In addition, local, on-chip voltageregulation is also needed, and this requires on-chip low-drop out (LDO)regulators. Activating a switch or realizing an LDO at voltage near VDD often requires circuits to operate in excess of the circuit's VDD, and this can be achieved using drain-extended (DE) CMOS, which can sustain voltage on the drain in excess of the BVDss of a normal MOSFET. DE CMOS can also be used to implement high-voltage battery charger circuitry in battery-operated products.
Over the past severalyears, tremendous progress had been made in implementing analog andpower management functions in deep submicron CMOS. Today, many analogfunctions required in a cellular handset can be implemented costeffectively in deep submicron digital CMOS. Consequently, SoCintegration, coupled with the DBB chip, offers an attractive path tocombined analog and power-management circuitry.
Radio integration
Theradio in a modern handset faces some severe performance requirements.Signals with amplitudes of only a few microvolts must be received inthe face of strong interferers, high output power levels (roughly 30dBm) must be produced to drive the antenna, and isolation betweenvarious radios within the handset must be accounted for. In addition,radio designs require accurate filtering at high frequencies and goodmatching between circuits in the signal path. These combinedrequirements make radio integration a considerable challenge and makethe choice of SiP vs. SoC for the radio function a complex decision.
Looking at the typicalfunctions found in a modern GSM radio, the transceiver contains thesmall-signal radio electronics needed for up- and down-converting theinformation signal to the transmission band (Fig. 2). The poweramplifier (PA) module amplifies the transceiver output to produce anoutput signal with adequate power for reliable transmission. Thefront-end (FE) module normally includes the RF switch function (forseparating the time-multiplexed transmit and receive signals) and theRF preselect filters which are normally surface acoustic wave (SAW)devices (the module can be partitioned in other ways, as well). Asimilar diagram would represent a cellular standard, such as CDMA, thatimplements full-duplex operation in the air interface. However, theswitch function would be replaced by a duplexer.
2. This high-level block diagram looks at a modern GSM radio.One possible partitioningoption for the radio electronics, an SoC, integrates the radIOTransceiver with the baseband processor. Alternatively, using SiPintegration, the transceiver could be integrated with the PA and FEmodules to create one analog radio module. Because interfacing theradio signals between analog functions normally requires matchingnetworks, many passive components are associated with the radio design.Consequently, it's advantageous to pull as many passive elements aspossible into the PA and FE modules. Normally, the PA and FE modulesremain separate to avoid thermal stability issues with the SAW filtersfrom being aggravated by the heat generated in the PA. However, somedesigns integrate the entire radio function into one package.
Ultimately, a discussionof SiP vs. SoC in the RF implementation comes down to whether thetransceiver is better integrated through packaging technology with theFE and/or PA module, or if it's better to integrate the transceivermonolithically with the baseband processor.
Because SiP allows use ofa conventional analog RF transceiver, no new transceiver architecturesor special IC technology is required. The transceiver capability iswell established and, apart from layout considerations associated withmodule integration (bond pad placement, IC aspect ratios, etc.), littlestands in the way of SiP integration. However, integrating thetransceiver also offers little in terms of improving the overallsystem. While board area may be reduced, no improvement in powerconsumption is gained and the overall system cost may increase.
SoC integration of thetransceiver is normally undertaken with monolithic integration in deepsubmicron CMOS. Alternatively, a BiCMOS (SiGe) wafer process might beused to implement a conventional radio architecture. However, theadditional reticles required for a SiGe wafer would drive up the costof the system logic and memory, and the lack of SiGe processes at stateof the art lithography would increase the logic area. Also, thebenefits associated with tightly coupling the system logic with theradio function wouldn't be fully realized if a conventional radio isemployed. Hence, monolithic integration in BiCMOS (or SiGe) isn't anattractive option.
Consequently, SoCintegration of the transceiver must be undertaken in CMOS. Fortunately,deep submicron CMOS transistors offer good RF performance and meet theneeds of integrated transceiver designs (low noise figures and hightransition frequencies are possible). However, conventional RFtransceiver designs make extensive use of analog components and requirehigh-performance passive elements. Producing such a design in CMOSwould normally require several additional processing steps to producethe resistors, capacitors, and inductors needed.
Given the tremendouslogic density and high clock speeds offered by deep submicron logicprocesses, however, it seems natural to look for ways to exploit thisprocess technology through SoC. Doing so may require developing newradio architectures for implementation in deep submicron CMOS, but itcan provide significant advantages. Foremost among them is the factthat, as advances in CMOS wafer processing produce faster switchingspeeds, it becomes possible to sample at higher rates. Oversampling ofthe input signal reduces noise aliasing problems and relaxes the inputnetworks design. More complex filtering can be added and A/D conversioncan occur closer to the antenna. In addition, SoC integration improvessystem yield because more of the system function is implemented aslogic (verses analog RF which suffers parametric yield loss). Movingthe radio function to an aggressively scaled technology also reducesboard area and total silicon area (Fig. 3).
3. A GSM device is shown with a fully integrated transceiver.A system as complex as a3G cellular handset may best be implemented with a combination of SiPand SoC technologies. For system memory, SoC integration may requireadditional reticle steps, and therefore be less cost-effective than SiPdie stacking. On the other hand, high-performance A/D and D/Aconverters and excellent power management have been realized with SoCintegration in CMOS.
For RF integration, a mixof SiP and SoC appears optimal. While power amplifiers, SAW filters, RFswitches, and their associated passive elements are best implemented asSiP modules, considerable benefits are gained from SoC integration ofthe RF transceiver function with the system baseband processor in deepsub-micron CMOS. RF SoC integration can reduce power, cost, board area,and test cost while improving performance, phone manufacturability andyield.
About the author
Peter Rickert, TI Fellow, is the director of ASP platformmanagement. He received a BSEE degree at Clarkson University. Rickertcan be reached at p-rickert@ti.com.Dr. Dennis Buss is the vice-president of silicon technologydevelopment at TI. He holds bachelor's, master's, and doctoral degreesin electrical engineering from MIT. Buss can be reached at buss@ti.com.Bill Krenik is a wireless advanced architectures manager inTI's wireless terminals business unit. He received a PhD in electricalengineering at the University of Texas, an MSEE degree at SouthernMethodist University, and a BSEE degree from the University ofMinnesota. Krenik can be reached at w-krenik@ti.com.p-rickert@ti.com. |
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