Low Power Architecture Exploration for ASIC Algorithm Implementation

godsnake

free
webniar link

http://www.techonline.com/learning/webinar/222002556?queryText=synopsys

On-Demand Webinar

登录/注册后可看大图

Low Power Architecture Exploration for ASIC Algorithm Implementation

Overview: With today's advanced low power design requirements it is becoming moreand more critical to have proper insight into power consumption earlyin the design flow. Algorithm and datapath-intensive designs often havearchitecture tradeoffs which have huge impact on the power profile ofthe implementation. Thus it is important to properly estimate the powerconsumption of these alternate architectures quickly and accurately, inaddition to analyzing the timing and area results. This webinar willdemonstrate using the Synphony high level synthesis tool to doarchitectural power exploration within days of a having a high levelalgorithm model in MATLAB or Simulink. The analysis includes timing,area, and power consumption of various multi-rate architectures usingDesign Compiler and PrimeTime-PX.