high-voltage ESD papers

bt01234 · 发表于 2010-1-10 22:57:42

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1. High-voltage nLDMOS in waffle-layout style with body-injected technique for ESD protection
2. Investigation on the validity of holding voltage in high-voltage devices measured by transmission-line-pulsing (TLP)
3. Source-side engineering to increase holding voltage of LDMOS in a 0.5-um 16-V BCD technology to avoid latch-up failure
4. Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection
5. Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

zhifj86 · 发表于 2010-1-11 10:15:03

抢个沙发~~~~~~~~~谢谢楼主分享

duduxy · 发表于 2010-1-11 10:49:23

下来看看

359705716 · 发表于 2010-1-11 12:42:56

thanks

cgxcgx2007 · 发表于 2010-1-11 12:47:18

ddddddddddddd

temp199 · 发表于 2010-1-11 13:41:34

Sweetlover · 发表于 2010-1-11 21:21:30

下来看看

baoerxing · 发表于 2010-1-16 20:49:58

正需要高压ESD的资料
多谢了

zhifj86 · 发表于 2010-1-17 14:45:39

have a look

yuxi · 发表于 2010-1-17 16:16:28

下来看看

[资料] high-voltage ESD papers

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