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ASIC P&R Engineer
泰鼎多媒体技术(上海)有限公司
公司行业: 电子技术/半导体/集成电路 计算机软件 公司性质: 外资(欧美)
公司规模: 150-500人
工作地点: 上海-徐汇区 招聘人数:若干
外语要求: 英语 学 历: 不限
职位描述
Job Description:
In this role you will be responsible for chip/block level floorplanning,power planning, timing-driven place and route, congestion analysis and repair, clock tree synthesis, timing closure and physical verification (DRC/LVS). Perform circuit custom layout design and power planning.
Job Requirement:
1. Experience in ASIC physical design (place and route, DRC/LVS, power distribution, etc.)
2. Be familiar with PR tools such as SOCE/Austra.
3. Be familiar with chip tape out flow.
4. Experienced in circuit custom layout design.
5. BS/MS degree in Electrical Engineering, or science related subject.
6. Good communication and teamwork skills.
联系方式
电子邮箱: resehr@gmail.com |
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