[LSI]高手的春天--Digital IC/ASIC Engineer, Sept.27,2010更新

lowpowerdesign

LSI全球研发中心在徐汇区顶级写字楼（周边房价六七万吧），标准美资企业，Fabless大公司，工作环境优秀，团队气氛友好，团结向上,薪水也很不错，有较多出国培训机会，向上空间大，对职业生涯大有裨益，进来还发股票（最近）。如果有意，请发送简历到lowpowerdesign@hotmail.com.

顺便提一下内推和猎头。公司的每招聘猎头推荐的人才都要一定的费用，而内推却没有。同时，公司相关部门是有成本考核指标的。所以内推的录用率高。同时，把简历给猎头，简历的安全系数不高，送到老板手里就麻烦了：）本来这些东西我不想说的，因为这个版上猎头不少。不过貌似这是“众人皆知的秘密”.

这个职位是内推，可以提高您的录用几率，而且简历安全系数高啊，你懂的......

1.DSP System Applications Engineering Manager--(Full, no position now)
This position is part of a growing team supporting our latest generation of DSP solutions for media gateway, cellular baseband, and video applications. This manager will support a team of system applications engineers working directly with major customers to assist with porting, integration and debugging of various software modules. Customer interaction includes both presales activities and issue management during development phases. Ability to work well with a variety of people and disciplines is required. Occassional travel to customer sites is expected.
Excellent communications skills in both Chinese and English are required.
Requirements
- 4 years experience as applications engineer or in product development
- Additional 2 years experience managing an engineering team
- Excellent written and verbal communications in both Chinese and English
- Embedded software development/debug experience
- General knowledge of communication technologies and protocols
Desired:
- Experience with media gateways, cellular baseband or video transcoding
- Specific experience with ARM processors and/or StarCore DSPs
- Previous interaction with major telecom vendors in China
Education

2. Digital IC Design Engineer(1)--要会写代码，懂电路，知道代码与综合出来的电路之间的映射关系，英语好
- Working with an Architecture/Algorithm Development Team to finalize system architecture for optimal implementation of digital signal processing algorithms, including architectural definition and tradeoffs, die size estimation.
- Digital logic design, verilog coding, logic synthesis, both RTL and gate level verification, formal verification and static timing analysis.
- Perform some transistor level high speed digital integrated circuit design various cells and blocks within custom chips for the hard disk drive industry. Examples of cells and blocks include multiplexors, adders, multipliers, dividers, specific functional macro blocks,
- Work very closely with physical design engineers from floorplan through final parasitic extraction to ensure smallest area and highest performance possible.
PREFERRED EXPERIENCE:
- Experience in logic design, synthesis, static timing analysis, and verification
- Experience with ASIC EDA tools used in synthesis, simulation, static timing analysis, and formal verification
- Experience in developing simulation and verification test benches
- Knowledge of Verilog/VHDL design languages
- Excellent technical troubleshooting and demonstrated problem solving skills

3. Senior ASIC Customer Engineer(3)--偏“后”，做网表生成后的工作
ASIC Customer Engineer has responsibility for a wide range of tasks, including chip floor planning, place and route, timing analysis, signal integrity, test, and design verification.Responsible for support and completion of designs from customer provided RTL or Gate level
netlist using the latest technologies.
Design completion tasks include
- Presales Support (die size support, memory generation, address customer questions and concerns.)
- RTL Analysis & Synthesis
- Physical Design Implementation (bonding, floor planning, power structure insertion, place and route, timing closure) using Synopsys Astro or ICC
- Test insertion using Mentor, LogicVision, or Virage tools
- Formal Verification (Verplex or Formality)
- Static Timing Analysis (Primetime and Primetime SI)
- Cross talk analysis
- Power verification
- DRC & LVS

细分：
a. RTL Analysis/Synthesis/STA: The ideal candidate should have strong skills for the front-end of design implementation which includes RTL Analysis, Synthesis Strategies, and STA setup for
complex ASIC environments. This would include strategies for power management.

b.Physical Design Implementation: The ideal candidate should be strong in either the Physical Design which includes floor planning, design closure, & STA. Having strong DRC & LVS skills are a plus. Strong Synopsys Astro/ICC experience a plus. Having strong Mentor Calibre skills a plus.

c.DFT: The ideal candidate should be strong in all DFT (Design for Test) for all aspects. This would include scan/TDF, TestKompress, MEMBIST/BISR, JTAG and etc… Having strong STA skills is a plus for timing for all aspects of test. Responsible for support / debug of customer designs after delivery of prototypes

pillar_chen

is it LSI?

lowpowerdesign

沙发没抢到，只好坐地板

不过这些都是好职位哦，如果够牛，就勇敢谈薪水吧！！

lowpowerdesign

不顶贴就会沉没
  
已经收到很多简历了

lowpowerdesign

收到了很多简历，每一封都做了相应的回复
  
这段时间是圣诞加元旦，很多hiring manager都休假，同时年终很多总结性质的工作，所以处理简历会慢一些
  
不过不要着急，请耐心等待，静候佳音

sjxu007

ASIC？

lowpowerdesign

这几天没有来顶帖，所以帖子沉了
  
大家知道，到了年终，hiring manager都很忙，所以处理简历速度可能会慢一些
  
同时呢，公司的部分高层是老美，或者在美国有亲人，他们要过圣诞节，所以这段时间来不及处理简历
  
但是，优秀的简历一定会被重视，所以请大家继续投简历。我会把简历给hiring manager和hr,谢谢！

vip

又是LSI？

lowpowerdesign

非常感谢各位的简历
  
每一封email我都仔细处理和回复过了，欢迎大家继续申请
  
最好使用哈佛大学商学院简历模版，这种模版做出来的简历最专业，容易被接受

frederick_gu

我來頂下