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[资料] ENERGY-EFFICIENT I/O INTERFACE DESIGN WITH ADAPTIVE POWER-SUPPLY REGULATION

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发表于 2009-12-21 01:55:55 | 显示全部楼层 |阅读模式

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ENERGY-EFFICIENT I/O INTERFACE DESIGN WITH ADAPTIVE POWER-SUPPLY REGULATION
by
Gu-Yeon Wei, STANFORD UNIVERSITY

Chapter 3 Digital Power-Supply Controller
Chapter 4 I/O Interface Design

gyw_thesis[1].pdf

1.37 MB, 下载次数: 143 , 下载积分: 资产 -2 信元, 下载支出 2 信元

发表于 2009-12-21 11:07:00 | 显示全部楼层
为啥不是全部呢?
 楼主| 发表于 2009-12-21 23:30:57 | 显示全部楼层
是全部的論文
只是show其中兩章得內容
发表于 2009-12-21 23:32:49 | 显示全部楼层
thanks for sharing!!!
发表于 2009-12-22 17:19:45 | 显示全部楼层
thanks
发表于 2009-12-24 19:20:22 | 显示全部楼层
谢了!!!!
发表于 2009-12-25 21:02:48 | 显示全部楼层
看看
讲IO的
 楼主| 发表于 2010-1-2 00:27:48 | 显示全部楼层
Chapter 1 Introduction.....................................
1.1 Low-Power Techniques.................................
1.2 CMOS Parallel Links ....................................
1.3 Organization ..................................................
Chapter 2 Background .....................................
2.1 Power and Delay in Digital CMOS Circuits .
2.2 Delay Tracking..............................................
2.2.1 Inverter-based tracking....................
2.2.2 Other non-ideal effects ....................
2.2.3 Delay Tracking Summary ...............
2.3 Adaptive power supply regulation ................
2.3.1 Buck Converter ...............................
2.3.2 PID Control Loop............................
2.4 Summary .......................................................
Chapter 3 Digital Power-Supply Controller...
3.1 A/D Conversion.............................................
3.2 Digital PID Control .......................................
3.3 Variable-Frequency Control..........................
3.4 Low-Power Control .......................................
3.5 Non-Linear Power Reduction Techniques ....
3.6 Summary .......................................................
Chapter 4 I/O Interface Design...........................................
4.1 Overview of parallel links ...................................................
4.1.1 Critical-path delay.................................................
4.1.2 Signal Integrity......................................................
4.2 Finding the “right” voltage..................................................
4.2.1 Summary ...............................................................
4.3 Transmitter Design..............................................................
4.3.1 High-Impedance Drivers .......................................
4.3.2 Impedance, Current and Slew-Rate Control .........
4.3.3 Transmitter Summary............................................
4.4 Receiver Design ..................................................................
4.4.1 Bandwidth-Tracking Preamplifier ........................
4.4.2 Regenerative Latch and Timing ............................
4.4.3 Receiver Summary ................................................
4.5 Timing Recovery.................................................................
4.5.1 Dual-loop architecture...........................................
4.5.2 Digital interpolation ..............................................
4.5.3 Duty-cycle adjuster ...............................................
4.5.4 Clock Distribution and Relative Timing...............
4.5.5 Timing Recovery Summary ..................................
4.6 Experimental Results...........................................................
4.6.1 Test-chip Components and Testing Circuitry .......
4.6.2 Dual-Loop DLL ....................................................
4.6.3 I/O Transceiver......................................................
4.6.4 Power Breakdown Analysis ..................................
4.7 Summary .............................................................................
Chapter 5 Conclusions .........................................................
发表于 2010-1-2 14:33:51 | 显示全部楼层
不错  谢谢
发表于 2010-1-19 17:05:41 | 显示全部楼层
Very GOOD!
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