Two Stanford Ph.D Papers About ADC Published in Second half year of 2008

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Two Stanford Ph.D Papers About ADC Published in Second half year of 2008

Analog-to-digital converters for high-speed links.
In today's technology, high-speed links play an important role, enabling faster, cheaper, and more reliable data communications. Data converters, present in some form in almost all modern high-speed links, are a key to performing equalization - the process of compensating bandwidth limitations of the communication channel. In particular, baud-rate ADCs at the receiver front ends can enable easily-scalable digital implementations of various equalization schemes, such as feed-forward equalization (FFE), decision-feedback equalization (DFE), and even maximum-likelihood sequence estimation (MLSE). However, power limitations of on-chip high-speed link receivers make front-end ADC design very challenging. Therefore, in this work we pay special attention to power efficiency of the ADCs and not only to their performance. This leads us to the idea of heavily interleaving very simple and efficient ADCs to obtain high aggregate conversion rates.;We choose a single-slope ADC as a candidate for interleaving because of its simplicity, linearity, low-power operation, small area, and small input capacitance. This choice is nevertheless unusual because of single-slope's reputation for long conversion time, normally taking 2Nbits time steps, where Nbits is the ADC resolution. However, because PLLs and/or DLLs in high-speed links normally generate very fine time steps, the conversion rates of single-slope ADCs for relatively low resolution can be pushed to Gsps range. We demonstrate the suitability of single-slope ADCs for high-speed low-power operation with a proof-of-concept design in the high-speed 45nm TI CMOS technology. In simulation, the ADC was capable of 4.5bit 1.6Gsps or 5.5bit 0.8Gsps operation while consuming 3mW of power from a 1V supply.;The prototype was, however, fabricated without redesign in a different, low-leakage, variant of 45nm technology. Due to differences in device characteristics, the chip operated at only 800MHz in a 4.5-bit mode and at 400MHz in a 5.5-bit mode while consuming 4mW from a 1.2V supply. Nevertheless, it lays groundwork for simple high-speed low-power ADCs based on a single-slope architecture.

Digital compensation of dynamic acquisition errors at the front-end of ADCs.

In Analog-to-Digital Converter (ADC) applications such as wireless base stations, sub-sampling at an Intermediate Frequency (IF) is an attractive method for minimizing component count and system cost. By applying this method, one or more steps of down-conversion are removed from the receiver path and some of the analog front-end signal processing functions can be moved to the digital domain. In such a solution, the ADC's linearity at high input frequencies becomes a critical issue. Despite the use of a dedicated track-and-hold amplifier (THA), nonlinearities in the circuit's input network often introduce dynamic errors that limit the performance of the ADC at high input frequencies.;A number of analog techniques have been proposed in the past to improve the linearity performance of the ADC's front-end. However, most of these techniques suffer from bandwidth limitations in the active analog circuitry and lose their performance at high input frequencies. In recent years, the continuous scaling of CMOS technology has resulted in low cost and high performance digital circuits. This has provided the feasibility to integrate complicated digital signal processing on chip and therefore use digital correction methods to compensate circuit nonlinearities in ADCs. However, these techniques mainly address static errors in the converter core and are not effective at removing dynamic nonlinearities at the front-end of the ADC.;This dissertation introduces a digital enhancement scheme that is specifically tailored to remove high frequency distortion caused by the dynamic nonlinearities at the sampling front-end of ADCs. The basic concept of digital compensation here is to apply the inverse nonlinear function to the digital output of the ADC in order to minimize its error over the desired frequency range. Conceptually, a nonlinear system with memory can be modeled with a Volterra series. However, the inverse Volterra series becomes very complex as the order of nonlinearity and memory in the system increases and it requires intensive computational power that is impractical even in today's fine-line technology. Our proposed algorithm uses information about the sources of nonlinearity and judicious modeling to simplify the digital post processing scheme.;The main sources of dynamic error at the front-end of ADCs are investigated and analyzed in order to find a compact model for frequency-dependent nonlinearities in this stage. This model is then used to build a nonlinear filter in the digital domain for compensating the nonlinearities. The coefficients of the filter are calibrated using training signals in the desired frequency region. The correction scheme can be effectively used for canceling nonlinearities across the whole input bandwidth of the ADC.;Measurement results from applying the proposed method to a 14-bit commercially available ADC are presented at different frequency ranges. The experimental results show an improvement in SFDR of the ADC to more than 83 dB up to input frequencies of 470 MHz. Measurement results show that the algorithm is not very sensitive to temperature variations and is also applicable to any sub-sampling ADC that suffers from linearity degradation at high input frequencies.

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