ESD Design Papers by prof. Ker Ming-Dou(Part 3)

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ESD Design Papers by prof. Ker Ming-Dou(Part 3)

Contents:
1. A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device
2. Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-
submicron CMOS process
3. Area-efficient layout design for CMOS output transistors
4. Decreasing-size distributed ESD protection scheme for broadband RF circuits
5. Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog
applications
6. Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes
7. Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35um silicide CMOS
process
8. Design optimization of ESD protection and latchup prevention for a serial IO IC
9. Electrostatic Discharge (ESD) protection for CMOS output buffer in scaled-down CMOS VLSI technology
10. Electrostatic discharge protection design for mixed-voltage CMOS IO buffers
11. ESD failure mechanisms of analog IO cells in a 0.18um CMOS technology
12. ESD implantations for on-chip ESD protection with layout consideration in 0.18um salidided CMOS technology
13. ESD protection design for IO cells with embedded SCR structure as power-rail ESD clamp device in nanoscale
CMOS technology
14. ESD protection design for mixed-voltage IO buffer with substrate-triggered circuit
15. ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage IO
interfaces with signal levels higher than VDD and lower than VSS
16. ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode
applications
17. ESD protection design to overcome internal damages on interface circuits of a CMOS IC with multiple separated
power pins
18. ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS ICs
19. Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS
technology
20. Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs
21. High-current characterization of polysilicon diode for electrostatic discharge protection in sub-quarter-
micron complementary metal oxide semiconductor technology
22. Improved output ESD protection by dynamic gate floating design
23. Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices
24. Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC
applications
25. Investigation on seal-ring rules for IC product reliability in 0.25-µm CMOS technology
26. Investigation on seal-ring rules for IC product reliability in 0.25um CMOS technology
27. Latchup-free fully-protected input ESD protection circuit for submicron CMOS ICs
28. Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit

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denap

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xiangxing_0123

very good, thanks!