A Simple 8-bit CPU designed in Max+PlusII___gdf version

kevinwjs

This processor was designed to be simple tocreate, for that reason there are only 4 registers, few basic logic commands,only the most necessary flags, and only 2^16 bytes of addressable memory. Thisdesign scheme led to it’s being single cycle RISC-like. All memory access,besides the normal stepping through the program, uses the AB registercombination for the memory address.
Because of the limited number of registers, this processor is severelycrippled in performance. This might be the worst part of its design. There is afifth, unaddressable register (FLAGS). It can be accessed and data can bestored in it using the commands Flags->A and A->Flags. Be warned,however, that the contents of Flags will be erased if an opcode writes toFlags. The instruction format is the standard “Opcode Operand, Operand”. Due tothe 8 bit limit on opcode size, the only way to achieve a “load immediatevalue” command was to have it only accept small immediate values (4 bits).There is a Load Upper and a Load Lower, so that in 2 clock cycles, an entire8bit immediate value can be stored in the A register.
Load and Store currently do not operate correctly because ofmemory access conflicts with the IFU.

kevinwjs

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2009-12-7 20:34 上传

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zh123456789

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alexpanait

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xlteam21

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apptone

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wangoohu

thx for sharing....