Cadence: Analog Design Environment Lab & Lecture Manual Ver. 5.0

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Cadence: Analog Design Environment Lab & Lecture Manual Ver. 5.0

Modeul 1 Introduction
   Lab 1-1 Getting Started 1-1
   Lab 1-2 Top-Down System Modeling 1-5

Module 2 Schematic Capture
  Lab 2-1 Schematic Entry 2-1
  Lab 2-2 Symbol Creation 2-8
  Lab 2-3 Building the Supply Circuit  2-13
  Lab 2-4 Building the ampTest Design  2-17

Module 3 Analog Simulation with Spectre Direct
  Lab 3-1 Running Simulation 3-1
  Lab 3-2 Using the Stimulus Template
  Lab 3-3 Transient Operating Point Analysis, “infomations”
  Lab 3-4 Captab 3-27

Module 4 Displaying Simulation Results
  Lab 4-1 Displaying Results with the Waveform Windows 4-1
  Lab 4-2 Saving the Simulation Session 4-16
  Lab 4-3 Displaying Interpreted Labels Near Schematic Component 4-20
  Lab 4-4 Annotating Simulation Results to the Schematic Windows 4-25
        
Module 5 Analyzing Simulation Results
  Lab 5-1 The Waveform Calculator 5-1
  Lab 5-2 Managing Simulation Results 5-10
  Lab 5-3 Managing Simulation Data with the Results Browser 5-18
  Lab 5-4 Viewing Circuit Conditions 5-22
  Lab 5-5 Using the Spectre Sweep  5-28
Lab 5-6 Stability Analysis 5-37

Module 6 Using OCEAN and SKILL
  Lab 6-1 Using an OCEAN Script to Run a Simple Simulation  6-1
  Lab 6-2 Measuring PSRR and CMRR with OCEAN 6-11
  Lab 6-3 Introduction to SKILL 6-18
  Lab 6-4 SKILL Development Tools 6-24

Module 7 Parametric Analysis Tool
  Lab 7-1 Running Parametric Analysis 7-1

Module 8 Corners Analysis Tool
  Lab 8-1 Using the Corners Analysis Tool 8-1

Module 9 Monte Carlo Analysis
  Lab 9-1 Monte Carlo Analysis 9-1

Module 10 Circuit Optimization Tool
  Lab 10-1 Running Optimization Analysis 10-1

Module 11 Exploring CDF
  Lab 11-1 The CDP User Interface 11-1
  Lab 11-2 CDP Effects in Simulation 11-11

Module 12 Inline Subcircuits
  Lab 12-1 Creating a Parasitic Transistor Model 12-1
  Lab 12-2 Using Subcircuit Cells 12-9
  Lab 12-3 Adding a Subcircuit Representation 12-9

Module 13 Inherited Connections
  Lab 13-1 Inherited Connections 13-11
  Lab 13-2 Using Inherited Connections with the ampTest Design 13-10

Module 14 Hierarchy Editor
  Lab 14-1 Creating a Configuration File with the Hierarchy Editor 14-1
  Lab 14-2 Running a Simulation with Subcircuits 14-5
  Lab 14-3 Rerunning Simulation with the Schematic View 14-8

Module 15 Parasitic Simulation Setup
  Lab 15-1 Simulating a Schematic Without Parasitics 15-1

Module 16 Parasitic Simulation Setup and Analysis
  Lab 16-1 Parasitic Simulation Flow 16-1

Appendix A Diva Parasitic Extraction and Simulation
  Lab A-I Simulating a Schematic with Parasitics Using the Diva Layout Flow A-1

Appendix B Using the WaveScan Tool
        Lab B-1 Using the WaveScan Tool B-1

Appendix C Spectre MOL
  Lab C-I Using Spectre MDL C-1

Appendix DUsing "dcmatch" Analysis
   Lab D-l dcmatch D-1

Appendix E Advanced Topics
  Lab E-l Verilog-A Overview E-1

hi_china59

Cadence Analog Design Environment Lecture Manual

silentgun

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girubak

Xie Xie

girubak

thank you

girubak

Kan Kan

girubak

Thank you

girubak

Xie XIe

girubak

Kan Kan