VHDL 的一些 SAMPLES CODE 很不錯哦!

boblin0319

LBSALE[50]LBSALE這是一本電子書! 有很多例子

easy4880

我买了！！

lovetingting

都有些什么sample啊？？？

wjyok

i cant download why

zhdang

说说怎么样？

hoohooplay

http://www.eetop.com.cn/non-cgi/usr/5/5_1892.pdf

hoohooplay

http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html

hoohooplay

Examples of VHDL Descriptions
  
Advanced Electronic Design Automation
  
Examples of VHDL Descriptions
  
Author:  Ian Elliott of Northumbria University
This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinational logic, described in
terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any IEEE compliant VHDL simulator and many can be
synthesised using current synthesis tools.
Use the hierarchical links below to navigate your way through the examples:
●     Combinational Logic
●     Counters
●     Shift Registers
●     Memory
●     State Machines
●     Registers
●     Systems
●     ADC and DAC
●     Arithmetic
Combinational Logic
●     Exclusive-OR Gate (Dataflow style)
●     Exclusive-OR Gate (Behavioural style)
●     Exclusive-OR Gate (Structural style)
●     Miscell aneous Logic Gates
●     Three-input Majority Voter
●     Magnitude Comparator
●     Quad 2-input Nand (74x00)
●      BCD to Seven Segment Decoder
●     Dual 2-to-4 Decoder
●     Octal Bus Transceiver
●     Quad 2-input OR
●     8-bit Identity Comparator
●     Hamming Encoder
●     Hamming Decoder
●     2-to-4 Decoder with Testbench and Configuration
●     Multiplexer 16-to-4 using Selected Signal Assignment Statement
●     Multiplexer 16-to-4 using Conditional Signal Assignment Statement
●     Multiplexer 16-to-4 using if-then-elsif-else Statement
●     M68008 Address Decoder
●     Highest Priority Encoder
●     N-iCountersnput AND Gate
Universal Register
Description - This design is a universal register which can be used as a straightforward storage register, a bi-directio
and the mode is controlled by a 3-bit input. The 'termcnt' (terminal count) output goes high when the register contain
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY unicntr IS
   GENERIC(n : Positive := 8);   --size of counter/shifter   
   PORT(clock, serinl, serinr : IN Std_logic;   --serial inputs
        mode : IN Std_logic_vector(2 DOWNTO 0);   --mode control
        datain : IN Std_logic_vector((n-1) DOWNTO 0);   --parallel inputs
        dataout : OUT Std_logic_vector((n-1) DOWNTO 0); --parallel outputs
        termcnt : OUT Std_logic);    --terminal count output
END unicntr;
ARCHITECTURE v1 OF unicntr IS
   SIGNAL int_reg : Std_logic_vector((n-1) DOWNTO 0);
BEGIN
   main_proc : PROCESS
   BEGIN
      WAIT UNTIL rising_edge(clock);
         CASE mode IS
            --reset
            WHEN "000" => int_reg <= (OTHERS => '0');
            --parallel load
            WHEN "001" => int_reg <= datain;         
            --count up
            WHEN "010" => int_reg <= int_reg + 1;     
            --count down
            WHEN "011" => int_reg <= int_reg - 1;   
            --shift left
            WHEN "100" => int_reg <= int_reg((n-2) DOWNTO 0) & serinl;     
            --shift right
            WHEN "101" => int_reg <= serinr & int_reg((n-1) DOWNTO 1);     
            --do nothing
            WHEN OTHERS => NULL;
         END CASE;
   END PROCESS;
   det_zero : PROCESS(int_reg) --detects when count is 0
   BEGIN
      termcnt <= '1';
      FOR i IN int_reg'Range LOOP
http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html (3 of 67) [23/1/2002 4:15:08 ]

wxd314

好

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