求助，BGR测试结果分布比较散

thewolftotem

Hi  lakeoffire
感谢回复
我不明白的一些地方
1. 怎么得到delta beta和delta Vth值？输出netlist没有这两项，是工艺上的参数吗？
2. 这个Vos的表达式怎么推出来的，有参考资料吗？减小Vgs-Vth会使输入管进亚阈区，这样来减小Vos是否可行？
3. 我这里的unit resistor 是 9um/1um，这个面积应该不小了吧？

thewolftotem

还有三个电阻在版图上如何匹配最理想。R1=R2.R1/R0=9.

steve_guo_1997

感觉这个bgr设计参数上确有商榷的地方。
失调参数在design rule上会给出，不过不是每个process都提供的。

magicdog

考虑下流过diode的电流,如果采用1:8,流过的电流是0.4uA
对于8个diode来说每个diode只有0.05uA的电流
在这个电流下还满足所谓的指数定理吗?

如果你的工艺很稳定 pdk很准确 确实可以一定程度依赖simulation
如果工艺不是很ok 有些情况simulation是不够的

lakeoffire

Hi  lakeoffire
感谢回复关闭
我不明白的一些地方
1. 怎么得到delta beta和delta Vth值？输出netlist没有这两项，是工艺上的参数吗？
2. 这个Vos的表达式怎么推出来的，有参考资料吗？减小Vgs-Vth会使输入管进亚阈区 ...
thewolftotem 发表于 2009-11-20 15:09

                               
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1. Some design rules provide mismatch parameters for two devices in term of (delta_beta/beta), detal_vth, (delta_R/R).
2. Typically, offset voltage could be treated like noise. For each transistor, you could derive delta_Id in term of delta_beta/beta and delta_Vth (referred to Razavi's book). Like noise analysis, the Vos could be calculated as delta_Id divided by the input gm. In this way, you know the variance of Vos in terms of variance of (delta_beta/beta) and delta_vth, which in turn are functions of the area of transistors. As you said, you could not reduce (Vgs-Vth) too much, and you will end up with increase device size.
3. Similarly, the bandgap voltage variance is a function of the variance of (delta_R/R), which again could be reduced by increase the area of R. What I meant is that resistors with W/L and 4W/4L will have the same value, but the latter will provide much better matching and hence smaller contribution to bandgap output voltage variance.