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library ieee;
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您需要 登录 才可以下载或查看,没有账号?注册  use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 entity led_test3 is
 port(clk:in std_logic;
 rst:in std_logic;
 seg
  ut std_logic_vector(6 DOWNTO 0); bt
  ut STD_LOGIC_vector(3 downto 0) );
 end;
 architecture beh of led_test3 is
 signal cnt:std_logic_vector(1 downto 0);
 signal a:integer range 0 to 3;
 begin
 p1:process(clk,rst)
 begin
 if rst='1' then
 cnt<="00";
 elsif clk'event and clk='1' then
 cnt<=cnt+1;
 end if;
 end process p1;
 --- bt 是 位选端 seg为段选,数码管为共阳的 我想当clk为1hz时让四个数码管依次显示0,1,2,3;可是结果下到板子上他不是依次显示0,1,2,3;而是乱跳着显示不是每一秒钟从左往右依次显示
 p2:process(cnt)
 begin
 case cnt is
 when "00" => bt<="1000";a<=0;--
 when "01" => bt<="0100";a<=1;--223
 when "10" => bt<="0010";a<=2;--221
 when "11" => bt<="0001";a<=3;--230
 when others => null;
 end case;
 
 end process p2;
 p3:process(a)
 begin
 case a is
 when 0 => seg<="0000001";       -- display 0
 when 1 => seg<="1001111";       --1
 when 2 => seg<="0010010";       --2
 when 3 => seg<="0000110";       --3
 when others => null;
 end case;
 end process p3;
 end;
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