经典:DEDICATED DIGITAL PROCESSORS

teradyne

DEDICATED DIGITAL PROCESSORS
Methods in Hardware/Software System Design
F. Mayer-Lindenberg
Technical University of Hamburg-Harburg, Germany

1 Digital Computer Basics 1
1.1 Data Encoding 1
1.1.1 Encoding Numbers 3
1.1.2 Code Conversions and More Codes 7
1.2 Algorithms and Algorithmic Notations 9
1.2.1 Functional Composition and the Data Flow 10
1.2.2 Composition by Cases and the Control Flow 11
1.2.3 Alternative Algorithms 13
1.3 Boolean Functions 14
1.3.1 Sets of Elementary Boolean Operations 14
1.3.2 Gate Complexity and Simplification of Boolean Algorithms 16
1.3.3 Combined and Universal Functions 18
1.4 Timing, Synchronization and Memory 19
1.4.1 Processing Time and Throughput of Composite Circuits 20
1.4.2 Serial and Parallel Processing 22
1.4.3 Synchronization 25
1.5 Aspects of System Design 29
1.5.1 Architectures for Digital Systems 29
1.5.2 Application Modeling 31
1.5.3 Design Metrics 35
1.6 Summary 37
Exercises 38
2 Hardware Elements 41
2.1 Transistors, Gates and Flip-Flops 41
2.1.1 Implementing Gates with Switches 41
2.1.2 Registers and Synchronization Signals 50
CONTENTS ?vi
2.1.3 Power Consumption and Related Design Rules 57
2.1.4 Pulse Generation and Interfacing 61
2.2 Chip Technology 67
2.2.1 Memory Bus Interface 69
2.2.2 Semiconductor Memory Devices 71
2.2.3 Processors and Single-Chip Systems 76
2.2.4 Configurable Logic, FPGA 78
2.3 Chip Level and Circuit Board-Level Design 86
2.3.1 Chip Versus Board-Level Design 88
2.3.2 IP-Based Design 91
2.3.3 Configurable Boards and Interconnections 91
2.3.4 Testing 94
2.4 Summary 96
Exercises 96
3 Hardware Design Using VHDL 99
3.1 Hardware Design Languages 99
3.2 Entities and Signals 101
3.3 Functional Behavior of Building Blocks 102
3.4 Structural Architecture Definitions 106
3.5 Timing Behavior and Simulation 107
3.6 Test Benches 109
3.7 Synthesis Aspects 111
3.8 Summary 112
Exercises 113
4 Operations on Numbers 115
4.1 Single Bit Binary Adders and Multipliers 115
4.2 Fixed Point Add, Subtract, and Compare 116
4.3 Add and Subtract for Redundant Codes 120
4.4 Binary Multiplication 122
4.5 Sequential Adders, Multipliers and Multiply-Add Structures 124
4.6 Distributed Arithmetic 128
4.7 Division and Square Root 130
4.8 Floating Point Operations and Functions 131
4.9 Polynomial Arithmetic 133
4.10 Summary 134
Exercises 135
5 Sequential Control Circuits 137
5.1 Mealy and Moore Automata 137
5.2 Scheduling, Operand Selection and the Storage Automaton 140
5.3 Designing the Control Automaton 142
5.4 Sequencing with Counter and Shift Register Circuits 144
5.5 Implementing the Control Flow 146
CONTENTS ?vii
5.6 Synchronization 148
5.7 Summary 148
Exercises 149
6 Sequential Processors 151
6.1 Designing for ALU Efficiency 153
6.1.1 Multifunction ALU Circuits 153
6.1.2 Pipelining 158
6.2 The Memory Subsystem 159
6.2.1 Pipelined Memory Accesses, Registers, and the
Von Neumann Architecture 160
6.2.2 Instruction Set Architectures and Memory Requirements 162
6.2.3 Caches and Virtual Memory, Soft Caching 165
6.3 Simple Programmable Processor Designs 168
6.3.1 CPU1 – The Basic Control Function 168
6.3.2 CPU2 – An Efficient Processor for FPGA-based Systems 172
6.4 Interrupt Processing and Context Switching 179
6.5 Interfacing Techniques 182
6.5.1 Pipelining Input and Output 182
6.5.2 Parallel and Serial Interfaces, Counters and Timers 183
6.5.3 Input/Output Buses 185
6.5.4 Interfaces and Memory Expansion for the CPU2 192
6.6 Standard Processor Architectures 193
6.6.1 Evaluation of Processor Architectures 193
6.6.2 Micro Controllers 194
6.6.3 A High-Performance Processor Core for ASIC Designs 198
6.6.4 Super-Scalar and VLIW Processors 199
6.7 Summary 203
Exercises 203
7 System-Level Design 205
7.1 Scalable System Architectures 205
7.1.1 Architecture-Based Hardware Selection 205
7.1.2 Interfacing Component Processors 206
7.1.3 Architectures with Networking Building Blocks 208
7.2 Regular Processor Network Structures 211
7.3 Integrated Processor Networks 218
7.4 Static Application Mapping and Dynamic Resource Allocation 221
7.5 Resource Allocation on Crossbar Networks and FPGA Chips 224
7.6 Communicating Data and Control Information 226
7.7 The π-Nets Language for Heterogeneous Programmable Systems 228
7.7.1 Defining the Target System 230
7.7.2 Algorithms and Elementary Data Types 232
7.7.3 Application Processes and Communications 235
7.7.4 Configuration and Reconfiguration 238
7.7.5 Hardware Targets 240
CONTENTS ?viii
7.7.6 Software Targets 243
7.7.7 Architectural Support for HLL Programming 244
7.8 Summary 247
Exercises 247
8 Digital Signal Processors 249
8.1 Digital Signal Processing 249
8.1.1 Analog-to-Digital Conversion 249
8.1.2 Signal Sampling 251
8.1.3 DSP System Structure 253
8.2 DSP Algorithms 255
8.2.1 FIR Filters 256
8.2.2 Fast Fourier Transform 257
8.2.3 Fast Convolution and Correlation 260
8.2.4 Building Blocks for DSP Algorithms 261
8.3 Integrated DSP Chips 263
8.4 Integer DSP Chips – Integrated Processors for FIR Filtering 266
8.4.1 The ADSP21xx Family 267
8.4.2 The TMS320C54x Family 270
8.4.3 Dual MAC Architectures 271
8.5 Floating Point Processors 273
8.5.1 The Sharc Family 273
8.5.2 The TMS320C67xx Family 276
8.6 DSP on FPGA 279
8.7 Applications to Underwater Sound 279
8.7.1 Echo Sounder Design 280
8.7.2 Beam Forming 283
8.7.3 Passive Sonar 286
8.8 Summary 288
Exercises 289

[ 本帖最后由 teradyne 于 2006-7-2 10:15 编辑 ]

merkury

所在的用户组无法下载或查看附件

outside

Methods in Hardware/Software System Design,so many issues in one book?

gen2gen

东西是好，但是没有钱呀^_^

zxh-12

支持一下了

saniuduo

好书,我喜欢.

saniuduo

好书,我喜欢,我没有钱,我灌水.

dsp2008

已下，谢谢楼主。

zy_sh_npk

好东西，看看！