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请问一个IO口定义为 inout时,信号冲突的问题
描述:当MCU向FPGA发出读取EEPROM信号时,在“MCU-ALE”信号为低时将IO口的数据锁存到A0-A7,在ALE上升沿将“29040 CE”置0,在MCU_RD线的下降沿将“8位双向IO口”置为高阻态,在RD的上升沿表示数据读取完毕,恢复初始状态,
程序:
addr_latch_Proc: process ( MCU_ALE,MCU_ALE_r)
begin
if (MCU_ALE='0' and MCU_ALE_r='1') then
A_latch <= RBR;
elsif (MCU_ALE='1'and MCU_ALE_r='0') then
CE_29040<='0';
end if ;
if (MCU_RD='0' and MCU_RD_r='1')then
RBR<="ZZZZZZZZ" ;
elsif (MCU_RD='1' and MCU_RD_r='0') then
CE_29040<='1';
RBR <=(others => '0');
end if ;
end processaddr_latch_Proc;
综合后:
WARNING:Xst:638 - in unit eeprom_rw Conflict on KEEP property on signal Mtridata_rbr<5> and Mtridata_rbr<7>, Mtridata_rbr<7> signal will be lost.
WARNING:Xst:638 - in unit eeprom_rw Conflict on KEEP property on signal Mtridata_rbr<5> and Mtridata_rbr<6>, Mtridata_rbr<6> signal will be lost.
哪位遇到过这种情况啊,程序该怎么改才对呢? |
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