verilog example include simulation , behavior and RTL model

tmc7330 · 发表于 2009-10-3 10:41:18

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Example of :
. J-K Flip-Flop
. Shift Register
. Counter
. Adder
. Moore State Machine
. Mealy State Machine
. One-Hot State Machine for FPGAs
. Linear Feedback Shift Register (LFSR)
. Encrypter/Decrypter
. Phase Locked Loop (PLL)
. Unsigned Integer Multiplier
. Signed Integer Multiplier
. Parity Generator and Checker
. Hamming Code Logic
. Checksum
. Cyclic Redundancy Check (CRC)
. Random Access Memory (RAM)
. Dual Port RAM
. Synchronous FIFO
. Synchronizing FIFO
. SRAM/ROM Controller
. Synchronous SRAM Controller
. DRAM Controller
. Fast Page Mode DRAM Controller

mmiker · 发表于 2010-2-8 02:56:10

KANKAN.

colinsu · 发表于 2010-4-16 00:53:56

YES 謝謝. 很有用

chongyi199 · 发表于 2010-5-14 23:24:02

thank you for share

eecc · 发表于 2010-5-22 21:25:24

正好需要感謝大大分享

alexpanait · 发表于 2010-5-23 18:10:02

thank you

dally · 发表于 2010-5-23 23:54:47

Thanks for sharing

xd_hg · 发表于 2010-5-24 14:33:47

收下看看

yoshida2010 · 发表于 2010-5-25 20:57:26

thank you

yuanwolf2008 · 发表于 2010-5-25 21:38:15

谢谢分享

verilog example include simulation , behavior and RTL model

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