在线咨询 切换到宽版
eetop公众号 创芯大讲堂 创芯人才网

 找回密码
 注册

手机号码,快捷登录

手机号码,快捷登录

搜帖子
查看: 12105|回复: 43

[ebook]Network-on-Chip Architectures: A Holistic Design Exploration

[复制链接]
发表于 2009-9-21 11:23:42 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

×
[size=120%]Network-on-Chip Architectures: A Holistic Design Exploration (Lecture Notes in Electrical Engineering) By Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
  • Publisher: Springer
  • Number Of Pages: 223
  • Publication Date: 2009-10-01
  • ISBN-10 / ASIN: 9048130301
  • ISBN-13 / EAN: 9789048130306
Product Description: The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.]

[ 本帖最后由 pipiw 于 2009-9-21 21:31 编辑 ]
cover.jpg

Network-on-Chip Architectures.part1.rar

4.77 MB, 下载次数: 355 , 下载积分: 资产 -3 信元, 下载支出 3 信元

Network-on-Chip Architectures.part2.rar

3.11 MB, 下载次数: 357 , 下载积分: 资产 -2 信元, 下载支出 2 信元

发表于 2009-9-21 22:30:51 | 显示全部楼层
duoxie
回复 支持 反对

使用道具 举报

发表于 2009-9-25 02:45:01 | 显示全部楼层
Thanks for sharing
回复 支持 反对

使用道具 举报

发表于 2009-9-25 03:09:37 | 显示全部楼层
Thanks for sharing
回复 支持 反对

使用道具 举报

发表于 2009-9-25 11:23:28 | 显示全部楼层
thx for sharing
回复 支持 反对

使用道具 举报

发表于 2009-9-26 00:28:22 | 显示全部楼层
下来看看先
回复 支持 反对

使用道具 举报

发表于 2009-9-26 08:57:10 | 显示全部楼层
good, thanks.
回复 支持 反对

使用道具 举报

发表于 2009-9-26 08:59:36 | 显示全部楼层
good, thanks.
回复 支持 反对

使用道具 举报

发表于 2009-10-5 16:33:29 | 显示全部楼层
好书!!!!!!!!!!!!
回复 支持 反对

使用道具 举报

发表于 2009-10-5 16:37:10 | 显示全部楼层
看看!!!!!!!!!!
回复 支持 反对

使用道具 举报

您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条


手机版| 小黑屋| 关于我们| 联系我们| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2025-9-13 15:08 , Processed in 0.024529 second(s), 7 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表