Any fast method to checking floating node?

smartchi

Hi Folk,

Does C@dence provide any simulation method to check floating node (hidden floating node because of circuit design) of my circuit? Could you tell me how could I do it?

Thanks

smartchi

haharun

Hi, smartchi:
There are 2 phase of floating node checking:
First one is in front-end  phase:
HAL report, DC report, even elaboration warnings can give you a hint of floating node
You mentioned simulation method so I guess this should be what you want
Second one is in physical verification phase
When you do ERC checking, back-end tools can tell you if e.g. there is a transistor with floationg node.

Hope this helps

smartchi

Hi Haharun,


       Thanks for your reply. Could you tell me what is HAL? Moreover, you mention the backend method. Could you tell me more in detailed about this?

Thanks

smartchi

原帖由 haharun 于 2009-9-20 02:18 PM 发表

                               
登录/注册后可看大图

Hi, smartchi:There are 2 phase of floating node checking:First one is in front-end  phase:HAL report, DC report, even elaboration warnings can give you a hint of floating nodeYou mentioned sim ...

escorial

I use Debussy for such a task - it have feature to report all Z's in the design in the current simulation time. They are generally good candidates for the floating net's.
Of course you can use special Lint tools - nLint, HAL, Leda, HDL Designer.
Depending on you skills - DC, Quartus could be used for better synthesys checks (bus width mismatch, drive of an input port, busses merged to single bit due to implicit wire declaration etc).