我现在已经实现了一个计时单元，但是我想把输入信号延时“计时单元所计的时间”

yourazhe

该怎么办呢？？
我的计时单元程序为：
--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity delay300 is
generic(size : integer := 13);
    port (
        clk: in STD_LOGIC;
        reset : buffer STD_LOGIC;
        set : in STD_LOGIC;
        enable : in STD_LOGIC;
        q: buffer STD_LOGIC_VECTOR((size - 1) DOWNTO 0);
        delay300: out STD_LOGIC
        
        );
end delay300;
architecture delay300_arch of delay300 is

begin
counter : process(clk,reset)
begin

if (reset = '1') then
q <= (others => '0');
elsif (clk'event and clk = '1') then
if (set = '1') then
q <= "0000000000000";
elsif (enable = '1') then
q <= q +'1';
else
q <= q;

end if;
end if;
end process counter;
delay300 <= '1' when q >= "1011101110000"  else '0';
end architecture delay300_arch;

bravelu

可以检测上升沿开始计数，计到你的delay值后开始输出，再检测下降沿，测到后把计数值往下减，减为0时停止输出。