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发表于 2011-1-17 23:46:52
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The NPN BJT clamp has a 3 V CMOS driver with an NPN base directly connected
to the inverter output (Fig. 5.6a, b). Each clamp has an NPN with a total
emitter width of 540 μm. The RC-timer time constant is ∼6 μs.
The clamp provides an appropriate low leakage in the powering sequence
(Fig. 5.6e) and the desired single pulse waveform (Fig. 5.6c) with a low clamping
voltage, if the number of slave clamps is sufficiently high (Fig. 5.6c). The peak
amplitude of the waveform produced by the circuit is below 1 V and practically does
not change starting with ∼10 clamps (Fig. 5.6c). However, the voltage accumulation
effect is observed in the case of a multiple zap sequence through the I/O diodes
(Fig. 5.6d). |
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