Test Structures for Benchmarking the ESD Robustness of CMOS Technologies

esdlab

Test Structures for Benchmarking the Electrostatic Discharge (ESD)Robustness of CMOS Technologies
by Steven Voldman

Table of Contents
1 EXECUTIVE SUMMARY....................................................................................................... 1
2 OBJECTIVES...........................................................................................................................1
2.1Context.............................................................................................................................2
2.2 ProblemStatement............................................................................................................2
2.3Purpose.............................................................................................................................2
2.4Scope................................................................................................................................3
3 IMPLEMENTATION STRATEGY ......................................................................................... 3
3.1 StructureStrategy..............................................................................................................3
3.2 ESDMetrics......................................................................................................................4
3.3 Scaling..............................................................................................................................4
3.4 Testing..............................................................................................................................4
3.5 ESD Module Configuration Philosophy ........................................................................... 4
3.6Assumptions.....................................................................................................................4
3.7 Definitions and Conventions Used in This Document ..................................................... 5
4 ESD BENCHMARK STRUCTURES: RESISTOR BENCHMARK STRUCTURES............ 5
4.1 N-Well Resistor Structure................................................................................................. 5
4.2 N+ Diffusion Resistor Structure ....................................................................................... 7
4.2.1 N+ Diffusion Resistor with No Silicide Block ...................................................... 7
4.2.2 N+ Diffusion Resistor with Silicide Block ............................................................ 8
4.3 Polysilicon Resistor..........................................................................................................9
5 DIODE BENCHMARK STRUCTURES ............................................................................... 10
5.1 Single Finger P+ Diode................................................................................................... 11
5.2 Two Finger P+ Diode...................................................................................................... 13
5.3 Three Finger P+ Diode.................................................................................................... 15
5.4 N+ DiodeStructure.........................................................................................................16
5.5 N-Well Diode Structure .................................................................................................. 18
6 PARASITIC NPN BIPOLAR BENCHMARK STRUCTURES ............................................ 19
6.1 Non-Gated Thick-Oxide Well-Well Device/Parasitic .................................................... 19
6.2 Gated Thick Oxide Well-Well Device/Parasitic............................................................. 21
6.3 Non-Gated Thick Oxide N+ to Well Device/Parasitic ................................................... 22
6.4 Gated Thick Oxide N+ to N-Well Device/Parasitic ....................................................... 24
6.5 Non-Gated Thick Oxide N+ to N+ Device/Parasitic ...................................................... 25
6.6 Gated Thick-Oxide N+ to N+ Device/Parasitic.............................................................. 27
7 MOSFET BENCHMARK STRUCTURES............................................................................ 29
7.1 Single Finger N-Channel MOSFET................................................................................ 29
7.2 Multi-Finger N-Channel MOSFET................................................................................. 32
7.3 N-Channel MOSFETs with Integrated Resistors............................................................ 34
7.4 Single Finger P-Channel MOSFET ................................................................................ 36
7.5 Multi-Finger P-channel MOSFET .................................................................................. 38
7.6 Multi-Finger PMOS with Local Well Taps .................................................................... 40
8 SILICON CONTROLLED RECTIFIERS............................................................................... 42
8.1 Thick Oxide npn Triggered SCR .................................................................................... 43
8.2 Low Voltage N-Channel MOSFET Triggered SCR (LVTSCR).................................... 45
9 ESD MODULE/PAD CONFIGURATION............................................................................. 47
10 TABULATION OF THE ESD ROBUSTNESS OF THE TECHNOLOGY .......................... 47
11 GLOSSARY OF TERMS ....................................................................................................... 47
12 PAD CONFIGURATION....................................................................................................... 49
13REFERENCES.......................................................................................................................49
13.1 Diodes.............................................................................................................................49
13.2Resistors.........................................................................................................................49
13.3 MOSDevices..................................................................................................................49
13.4Interconnects..................................................................................................................50
13.5 SCRs...............................................................................................................................50
13.6 ParasiticDevices.............................................................................................................50
13.7 ProcessEffects................................................................................................................50
13.8 General Knowledge........................................................................................................51
13.9 Characterization and Testing .......................................................................................... 51

oxplorer

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s8553warrior

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charles2000k

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charles2000k

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