BSIM4.3.0 MOSFET Model

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Chapter 1: Effective Oxide Thickness, Channel Length and
Channel Width 1-1
1.1 Gate Dielectric Model 1-1
1.2 Poly-Silicon Gate Depletion 1-2
1.3 Effective Channel Length and Width 1-5
Chapter 2: Threshold Voltage Model 2-1
2.1 Long-Channel Model With Uniform Doping 2-1
2.2 Non-Uniform Vertical Doping 2-2
2.3 Non-Uniform Lateral Doping: Pocket (Halo) Implant 2-5
2.4 Short-Channel and DIBL Effects 2-6
2.5 Narrow-Width Effect 2-9
Chapter 3: Channel Charge and Subthreshold Swing Models 3-1
3.1 Channel Charge Model 3-1
3.2 Subthreshold Swing n 3-5
Chapter 4: Gate Direct Tunneling Current Model 4-1
4.1 Model selectors 4-2
4.2 Voltage Across Oxide Vox 4-2
4.3 Equations for Tunneling Currents 4-3
Chapter 5: Drain Current Model 5-1
5.1 Bulk Charge Effect 5-1
5.2Unified Mobility Model 5-2
5.3Asymmetric and Bias-Dependent Source/Drain Resistance Model 5-4
5.4 Drain Current for Triode Region 5-5
5.5 Velocity Saturation 5-7
5.6Saturation Voltage Vdsat 5-8
5.7Saturation-Region Output Conductance Model
5.8Single-Equation Channel Current Model 5-16
5.9 New Current Saturation Mechanisms: Velocity Overshoot and Source End Velocity Limit Model 5-17
Chapter 6: Body Current Models 6-1
6.1 Iii Model 6-1
6.2 IGIDL Model 6-2
Chapter 7: Capacitance Model 7-1
7.1 General Description 7-1
7.2Methodology for Intrinsic Capacitance Modeling 7-3
7.3Charge-Thickness Capacitance Model (CTM) 7-9
7.4Intrinsic Capacitance Model Equations 7-13
7.5Fringing/Overlap Capacitance Models 7-19
Chapter 8: High-Speed/RF Modelsm 8-1
8.1Charge-Deficit Non-Quasi-Static (NQS) Model 8-1
8.2Gate Electrode Electrode and Intrinsic-Input Resistance (IIR) Model 8-6
8.3Substrate Resistance Network 8-8
Chapter 9: Noise Modeling 9-1
9.1 Flicker Noise Models 9-1
9.2Channel Thermal Noise 9-4
9.3Other Noise Sources Modeled 9-7
Chapter 10: Asymmetric MOS Junction Diode Models 10-1
10.1Junction Diode IV Model 10-1
10.2Junction Diode CV Model 10-6
Chapter 11: layout-Dependent Parasitics Model 11-1
11.1 Geometry Definition 11-1
11.2Model Formulation and Options 11-3
Chapter 12: Temperature Dependence Model 12-1
12.1Temperature Dependence of Threshold Voltage 12-1
12.2Temperature Dependence of Mobility 12-1
12.3Temperature Dependence of Saturation Velocity 12-2
12.4Temperature Dependence of LDD Resistance 12-2
12.5Temperature Dependence of Junction Diode IV 12-3
12.6Temperature Dependence of Junction Diode CV 12-5
12.7Temperature Dependences of Eg and ni 12-8
Chapter 13: Stress Effect Model 13-1
13.1 Stress effect model development 13-1
13.2 Effective SA and SB for irregular LOD 13-2
Chapter 14: Parameter Extraction Methodology 14-1
14.1Optimization strategy 14-1
14.2 Extraction Strategy 14-2
14.3Extraction Procedure 14-3
Appendix A: Complete Parameter List A-1
A.1BSIM4.0.0 Model Selectors/Controllers A-1
A.2 Process Parameters A-3
A.3Basic Model Parameters A-5
A.4Parameters for Asymmetric and Bias-Dependent Rds Model A-10
A.5Impact Ionization Current Model Parameters A-11
A.6Gate-Induced Drain Leakage Model Parameters A-11
A.7Gate Dielectric Tunneling Current Model Parameters A-12
A.8Charge and Capacitance Model Parameters A-15
A.9High-Speed/RF Model Parameters A-17
A.10Flicker and Thermal Noise Model Parameters A-18
A.11Layout-Dependent Parasitics Model Parameters A-19
A.12Asymmetric Source/Drain Junction Diode Model Parameters A-20
A.13Temperature Dependence Parameters A-23
A.14dW and dL Parameters A-25
A.15Range Parameters for Model Application A-26
A.16 Notes 1-8 A-26

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