DIGITAL SWITCHING NOISE COUPLING IN MIXED-SIGNAL SYSTEM_ON_CHIP APPLICATIONS

mcbiz1

MEASUREMENT, SUPPRESSION, AND PREDICTION OF DIGITAL SWITCHING NOISE COUPLING IN MIXED-SIGNAL SYSTEM_ON_CHIP APPLICATIONS
作者：Cosmin Iorga

In system-on-chip (SoC) applications the digital switching noise propagates through
the substrate and power distribution networks to analog circuits, degrading their
performance. To overcome these interactions, measurement, suppression, and
prediction of noise coupling are essential. Measurements can help to monitor and
analyze the noise coupling distribution within the chip, suppression techniques reduce
the effect of noise coupling on analog circuits, and prediction allows the identification
of potential noise coupling issues before fabrication. This research work focuses on
all three aspects, by developing new and improved measurement techniques for
substrate and power supply noise, by proposing novel suppression methods based on
active noise cancellation, and by creating a modeling technique for early prediction of
noise coupling in architectural stages of the design.
The measurement work first identifies the importance to measure both substrate and
power supply noise, and not to affect the propagation or inject additional noise in the
substrate. A set of requirements is developed based on these aspects and on the
particularities of performing measurements in large and complex mixed-signal SoCs.
Driven by these requirements, a measurement technique is proposed based on small
and compact sensors that can easily be placed within high-density layout regions.
Their outputs are multiplexed and routed to an on-chip digitizing waveform recorder.
The sensors contain only PMOS transistors in a topology designed to minimally affect
the noise propagation, and not to inject additional noise. The on-chip digitizing
reduces the bandwidth limitation and signal contamination due to off-chip routing, and
eliminates additional analog output pins. Based on the experimental evaluation on a
0.13-μm CMOS test chip, bandwidth from DC to 1.6 GHz, linearity better than 1.5%
for substrate, and 6 % for power supply sensors have been achieved. Power supply
rejection of 64 dB has been achieved in substrate probing. The substrate noise
coupling into power supply probing was below detectable limits. Experimentally
reconstructed waveforms with 20 ps time resolution allowed the measurement of
amplitude, rise-time, and overshoot of transition edges.
The suppression work first discusses previous reported methods of reducing noise
generation, propagation, and reception by analog circuits. It is noticed that while these
methods reduce the noise coupling effect they don’t completely solve the problem.
For example, noise still exists inside guard rings, having magnitudes varying across
the region. To reduce even more the noise coupling effects, this research work
proposes three active cancellation structures that can be used in addition to
conventional guard ring methods. The first technique addresses the common-source
NMOS amplifier stage, and senses the substrate noise through a source-follower
PMOS transistor, which generates a noise cancellation current. The second technique
is a derivation of the first one for active loads made of a current source and a diodeconnected
transistor. The third technique addresses the NMOS in common-source
with degeneration configuration, and uses a negative feedback loop to cancel out the
substrate noise effect. The proposed substrate noise cancellation structures have been
evaluated in a 0.13 μm CMOS test chip. The active loads have been implemented in
the delay cells of a ring oscillator. Coupling reduction for the NMOS in commonsource
amplifier structure of 8.8 times has been achieved at 10 MHz sinusoidal
substrate noise, decreasing for higher frequencies to 5.6 times at 1 GHz. Coupling
reduction for NMOS common source with degeneration of 56 times has been achieved
at 10 MHz, decreasing to 10 times a 100 MHz, and to 1.5 times at 1 GHz. Ring
oscillator sideband suppression of 25 dB has been achieved at 1 MHz sinusoidal
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substrate noise, decreasing for higher frequencies to 4 dB at 600 MHz. The ring
oscillator frequency deviation has been reduced from 1% to 0.05% at 50 mV variation
of substrate potential, and from 5.5% to 0.8% at 250 mV.
The suppression work first discusses the noise coupling modeling and prediction in
SoCs, and the coverage of various stages of the design process. It is then noticed the
correlation between modeling accuracy and the stage of design where the methods can
be applied. Also, it is emphasized that the most accurate methods use the complete
layout which is available only late in the design process, and the problems found at
this stage often require major rework that significantly impacts cost and schedule.
Driven by the desire to predict the noise coupling problems early in the design
process, this work proposes a novel hybrid lumped-distributed model of the chip
substrate and power distribution integrated in a macro-model of the chip, package, and
PCB. The model has a two-dimensional and a simplified one-dimensional version.
Transient simulations and correlation with experimental measured data have been
performed on the one-dimensional model. Correlation of overshoot, two types of
ringing, and amplitudes has been achieved between the measured and simulated
waveforms. Correlation of frequency domain simulations between the one and twodimensional
models has also been achieved. Despite the fact that the accuracy is
lower than with the techniques using physical layout, or schematics and behavior
models, this approach can be used to predict major noise coupling issues during the
architectural stage of the design.

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