【新手求助】vhdl小程序

rambling

程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY half_adder IS
PORT(dataA, dataB: IN STD_LOGIC;
     sum: OUT STD_LOGIC;
     carry: OUT STD_LOGIC
);
END ENTITY half_adder ;
ARCHITECTURE dataflow OF half_adder IS
BEGIN
sum <= dataA XOR dataB;
carry <= dataA AND dataB;
END ARCHITECTURE dataflow;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY full_adder IS
PORT(dataA, dataB, carryin: IN STD_LOGIC;
     sum:OUT STD_LOGIC;
     carryout:OUT STD_LOGIC
);
END ENTITY full_adder;
ARCHITECTURE struct OF full_adder IS
COMPONENT half_adder
PORT(a,b : IN STD_LOGIC;
     s: OUT STD_LOGIC;
     ca: OUT STD_LOGIC
);
END COMPONENT;
SIGNAL u1sum, u1carry, u2carry : STD_LOGIC;
BEGIN
u1: half_adder PORT MAP(dataA, dataB, u1sum, u1carry);
u2: half_adder PORT MAP(u1sum, carryin,sum, u2carry);
carryout<= u2carry OR u1carry;
END ARCHITECTURE struct;

软件版本是：QUARTUS II 7.2
编译时报错：
Error: Port "a" does not exist in macrofunction "u2"
Error: Port "b" does not exist in macrofunction "u2"
Error: Port "ca" does not exist in macrofunction "u2"
Error: Port "s" does not exist in macrofunction "u2"
Error: Port "a" does not exist in macrofunction "u1"
Error: Port "b" does not exist in macrofunction "u1"
Error: Port "ca" does not exist in macrofunction "u1"
Error: Port "s" does not exist in macrofunction "u1"
Error: Quartus II Analysis & Synthesis was unsuccessful. 8 errors, 0 warnings
Info: Allocated 154 megabytes of memory during processing
Error: Processing ended: Fri Aug 07 09:04:14 2009
Error: Elapsed time: 00:00:01


路过的大狭帮帮忙吧，万分感谢！

Hanhaijngtao

已经确定是你元件例化声明、例化的问题。
half_adder定义部分和full_adder中half_adder的元件声明部分端口port 命名不一致。改成一样的就可以了！
比如把half_adder部分改成如下：（只改了端口声明部分）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY half_adder IS
PORT(a, b: IN STD_LOGIC;
     s: OUT STD_LOGIC;
     ca: OUT STD_LOGIC
);
END ENTITY half_adder ;
ARCHITECTURE dataflow OF half_adder IS
BEGIN
s <= a XOR b;
ca <= a AND b;
END ARCHITECTURE dataflow;

建议：元件例化的时候还是用名字映射的方法吧，很多书建议这个习惯的。