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Verilog-A language reference manual (june 2009)

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发表于 2009-8-2 21:39:47 | 显示全部楼层 |阅读模式

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verilog-a manual 2009.pdf

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发表于 2009-8-29 16:47:03 | 显示全部楼层
挺好的东西,咋没有人顶呢?
发表于 2009-8-29 18:46:08 | 显示全部楼层
thnsssssssss
发表于 2009-8-31 22:43:14 | 显示全部楼层
很需要,谢谢
发表于 2009-9-1 15:14:13 | 显示全部楼层
xiexiexiele
发表于 2009-9-2 13:54:04 | 显示全部楼层
Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS.
Verilog-A was created out of a need to standardize the Spectre behavioral language in face of competition from VHDL(an IEEE standard), which was absorbing analog capability from otherlanguages (e.g. MAST). Open Verilog International (OVI, the body thatoriginally standardized Verilog) agreed to support the standardization,provided that it was part of a plan to create Verilog-AMS — a singlelanguage covering both analog and digital design. Verilog-A was anall-analog subset of Verilog-AMS that was the first phase of the project.
Unfortunately, there was considerable delay between the first Verilog-A LRM and the full Verilog-AMS,and in that time Verilog moved to the IEEE, leaving Verilog-AMS behindat Accellera. Hence, the original goal of a single language standard isstill to be achieved.
发表于 2009-9-27 11:06:03 | 显示全部楼层
新版下载学习,希望有用
发表于 2009-9-27 13:14:15 | 显示全部楼层
谢谢LZ分享啊
发表于 2009-10-31 14:58:26 | 显示全部楼层
sdsdsdsdsdsdsdsd
发表于 2009-11-14 14:17:29 | 显示全部楼层
thanks a lot~~
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