XILINX FPGA布局布线时碰到NGDBuild错误

jamyce

求教！！！
XILINX Virtex-II芯片布局布线时碰到如下错误提示，请问原因是什么？如何解决？
Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:455 - logical net 'GND' has multiple drivers. The possible
   drivers causing this are pin G on block GND with type GND, pin PAD on block
   GND.PAD with type PAD
ERROR:NgdBuild:466 - input pad net 'GND' has illegal connection. Possible pins
   causing this are pin G on block GND with type GND

ZLS

你的输入扇出太多，被自动指定为全局时钟，你必修把输入连接到GCLK引脚上。

shaweikang1984

回复 2# ZLS


   输入扇出？？？