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这篇论文有详细的原理图,很容易就能上手设计CMOS图像传感器
Abstract
The implementation of active pixel based image sensors in CMOS technology is becoming
increasingly important for producing imaging systems that can be manufactured with low
cost, low power, simple interface, and with good image quality. The major obstacle in the
design of CMOS imagers is Fixed Pattern Noise (FPN) and Signal-to-Noise-Ratio (SNR)
of the video output. This research focuses on minimizing FPN and improving SNR in
linear CMOS image sensors which are needed in scanning and swiping applications such as
nger print sensing, spectroscopy, and medical imaging systems. FPN is reduced in this
research through the use of closed loop operational ampliers in active pixels and through
performing Correlated Double Sampling (CDS). SNR is improved by increasing the pixel
saturation voltage.
This thesis concludes that FPN can be reduced using the closed loop opamp buers.
The major FPN noise sources are the shot noise from the photodiode, kTC noise from the
sampling capacitors, and oset mismatches in the sample and hold ampliers all of which
are not compensated by CDS. Sample and hold amplier oset mismatch is identied as
the largest contributor to FPN.
The digital interface issues of CMOS imagers are also studied. The design of a 12-bit
pipelined analog-to-digital-converter (ADC) in standard CMOS technology is presented.
The integration of this ADC onto the imager chip would result in a digital image sensor.
Design of Low Noise, Low Power Linear CMOS Image Sensors.pdf
(1.27 MB, 下载次数: 1116 )
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