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Responsible for design of new line of consumer application processors. Tasks include RTL design, Synthesis, Timing Analysis, packaging and test insertion. Responsibilities also include supporting P&R group through physical design, supporting HW Engineering through silicon bringup, and supporting Product Engineering through silicon qualification and high volume production. Skills/Experience Requirement: -
BSEE required, MSEE preferred -
3+ years in ASIC design from concept through production -
Verilog RTL coding, Synthesis, Timing analysis experience -
Unix, scripting languages (Perl/Python) | 
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eetop公众号
创芯大讲堂
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发表于 2009-6-22 17:18:00
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