Abstract—This paper describes a 10 bit, 1.5 bit per stage
pipeline ADC. The ADC has a max sampling rate of 100 MHz, and
has been designed on a 0.25μ, 2.5V CMOS process. Several novel
design techniques have been introduced in order to address some
of the limiting factors in a state of the art ADC design. These
techniques have been verified in simulation, and an ENOB of 9.01
has been achieved.
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发表于 2009-5-4 09:00:25
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