The Verilog® Hardware Description Language-Fifth Edition

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The Verilog® Hardware Description Language,
Fifth Edition
Donald E. Thomas
ECE Department
Carnegie Mellon University
Pittsburgh, PA
Philip R. Moorby
Co-design Automation, Inc.
www.co-design.com

The Verilog language is a  hardware  description language  that  provides a  means of
specifying a digital system at a wide range of levels of abstraction. The language sup-
ports the early conceptual stages of design with its behavioral level of abstraction, and
the later  implementation  stages with its structural abstractions. The language includes
hierarchical constructs, allowing the designer to control a description’s complexity.
Verilog was originally designed in the winter of 1983/84 as a proprietary verifica-
tion/simulation product. Later, several other proprietary analysis tools were developed
around the  language,  including a fault  simulator and a  timing analyzer. More recently,
Verilog has  also  provided the  input  specification for  logic and  behavioral synthesis
tools. The Verilog  language has  been instrumental in  providing consistency across
these tools. The language was originally standardized as IEEE standard #1364-1995.
It has recently  been  revised and  standardized as IEEE standard  #1364-2001. This
book presents this latest revision of the language, providing material for the beginning
student and advanced user of the  language.

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