Design of High-Voltage-Tolerant ESD Protection

semico_ljj

Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 1, MARCH 2009

Ming-Dou Ker, Fellow, IEEE, and Chang-Tzu Wang, Student Member, IEEE

Abstract—Two new electrostatic discharge (ESD) protection
design by using only 1 × VDD low-voltage devices for mixedvoltage
I/O buffer with 3 × VDD input tolerance are proposed.
Two different special high-voltage-tolerant ESD detection circuits
are designed with substrate-triggered technique to improve ESD
protection efficiency of ESD clamp device. These two ESD detection
circuits with different design concepts both have effective
driving capability to trigger the ESD clamp device on. These ESD
protection designs have been successfully verified in two different
0.13-μm 1.2-V CMOS processes to provide excellent on-chip ESD
protection for 1.2-V/3.3-V mixed-voltage I/O buffers.

Index Terms—Electrostatic discharge (ESD), low-voltage
CMOS, mixed-voltage I/O, substrate-triggered technique.

semico_ljj

Area-Efficient ESD-Transient Detection Circuit With
Smaller Capacitance for On-Chip Power-Rail
ESD Protection in CMOS ICs

Shih-Hung Chen and Ming-Dou Ker, Fellow, IEEE

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 5, MAY 2009

pper1983

好东西，现在BCD的工艺很火暴啊。

zhfhit

最近在做高压的东西，希望能有帮助

pppwww

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ez123

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ez123

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IVER

good....

juhao0122

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jotaro1111

seems usesful