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SoC Design Engineer, or Senior Engineer
Key Responsibilities:
- Preparation and review of functional and design specification for SoC (ASIC/FPGA)
- Prove logical functionality and ASIC/FPGA code design/implementation.
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Coding of SoC functionality form top-level down to blocklevel - Verification and simulation of needed functionality on block level
- Make test plan and test strategy. Ensure effective testing and high quality product delivery.
- Participate in system requirement and architecture review.
- Generating the test bench environment for the verification
- Responsible for test planning, test case definition.
- Responsible for test environment setup and test automation tool implementation
- Prepare and review System-on-Chip development documentations and application documents
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Working as the technical point of contact on the ASIC/FPGAarea. Job Requirements:
SoC development & Methodology
- 3+ years of SoC (ASIC/FPGA) design experience
- Very good VHDL/Verilog knowhow and coding and modeling experience
- Complete understanding of the SoC (ASIC/FPGA) design flow and process.
- Knowledge of SoC (ASIC/FPGA) design and verification tools.
System
One to Two skills as mentioned below is required: - Solid background in Cellular networks and 2G and 3G technology
- Good knowledge on TDM and Packet (IP/Ethernet) based telecommunication network solution
- Microwave radio transport and related telecommunication network solution knowhow
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Detailed understanding of SDH and PDH technology andinterfaces Experience
- 3+ years experience in the R&D of Telecommunication Networks or Communication industry.
Education/Skills
- Bachelor/Master of Science (Electrical Engineering)
- Innovative thinking and team working spirit.
- Be initiative, capable to analyze and learn
- High team and result orientation are required.
- Know how to share knowledge with other colleagues.
- Fluent speaking and writing skills in English
工作地点可以在上海和杭州之间选择,主要开发网络或无线通信类的芯片, 有意向的朋友把简历发到 ubuntu-8.10@163.com
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发表于 2009-4-16 22:14:52
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