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Hi, currently i am working on PCIE PHY TX eye measurement during PCIE workshop but unluckily there are lots of jitter being detected in the transmitter eye. I have used the jitter analysis tool to further breakdown the jitter component using the LeCroy high speed sampling scope. It is found that the random jitter is pretty high ~ 15ps. This number will be multiplied by 14.1 to meet the BER=10E-12 if using dual-dirac model. To meet this BER, the eye has been closed to almost half of the UI due to the random jitter. Can someone give me a hint what will make the chip to have too huge random jitter? |
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jitter breakdown and transition eye
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