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发表于 2004-3-4 20:58:30
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求教:Verilog HDL
1不能
2
module ram256x8 (data, address, we, inclock, outclock, q);
input [7:0]data;
input [7:0]address;
input we, inclock, outclock;
output [7:0]q;
lpm_ram_dq inst_1 (.q (q), .data (data), .address (address),
.we (we), .inclock (inclock),
.outclock (outclock));
defparam inst_1.lpm_width = 8;
defparam inst_1.lpm_widthad = 8;
endmodule |
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