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发表于 2009-3-16 16:12:20
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Timing Optimization by Replacing Flip-Flops to Latches
简介atch circuits have advantage for timing and are widely used fur high-speed custom circuits. However, ASIC design flows are h don the circuits with flip-flops. Then, ASIC designers don't use latches. This paper describes a new timing optimization algorithm for ASIC by replacing flip-flops to latches without changing the functionality of the circuits. After latch replacement, mstricted retiming called fixed-phase retiming is carried out for timing optimization by minimizing the impact of clock skew and jitter. The experimental results show that 17% delay improvement of the benchmark circuits is achieved by proposed algorithms. |
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