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Session 5 Overview
Potpourri: PLL, Optical, DSL
Chair: Larry DeVito, Analog Devices, Wilmington, MA
Associate Chair: Miki Moyal, Intel, Haifa, Israel
High-bandwidth communication applications call for some common enabling circuit building blocks. In
particular, timing control and clock generation are critical functions of the transceivers that comprise
chip-to-chip, board-to-board and system-wide data links.
Paper 5.1 [National Chiao Tung University] describes an all-digital frequency synthesizer capable of selfupdating
its digital loop filter to simultaneously provide a quick locking time as well as low jitter generation
for its 10GHz clock output. Paper 5.2 [National Taiwan University, Industrial Technology Research
Institute] shows a new circuit idea using subharmonic injection locking for radically lower jitter in a frequency
multiplier PLL. Paper 5.3 [IBM T. J. Watson] shows a frequency-multiplier digital PLL which has
wide tuning range and small die area, and also avoids the uncontrolled gain problem of a BB phase detector
in an integer-N synthesizer resulting in lower jitter generation than the more common technique of
fractional-N synthesizer. Paper 5.4 [HKUST] shows a simple and effective modification of an injectionlocked
divider which gives significantly larger locking range. Paper 5.5 [IBM T. J. Watson, IBM] shows
an all-digital core building block of a CDR which creates a pair of quadrature signals with arbitrary phase
relative to a single phase reference input.
已经搜索论坛，为首发
S5.part01.rar
(1.95 MB, 下载次数: 21 )
[ 本帖最后由 nuoan 于 2009-3-10 09:06 编辑 ] |
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发表于 2009-3-10 08:36:51
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