关于ARM中TLB锁存的问题？

tatsec

下面是ARM手册上的一段TLB lockdown procedure，看不太明白，请指点………… （其中  
的第二步，第三步有什么用?他只是锁存指令或数据到TLB，为什么要失效整个TLB，而且第  
二步是什么意思？）                                                              
   The normal procedure to lock down N TLB entries is as follows:  
1. Ensure that no processor exceptions can occur during the execution of this   
procedure, by disabling  
interrupts, and so on.  
2. If an instruction TLB or unified TLB is being locked down, write the approp  
riate version of register  
10 with base == N, index == N, and P == 0. If appropriate, also turn off facil  
ities like branch  
prediction that make instruction prefetching harder to understand.  
3. Invalidate the entire TLB to be locked down.  
4. If an instruction TLB is being locked down, ensure that all TLB entries are  
loaded which relate to any  
instruction that could be prefetched by the rest of the lockdown procedure. (P  
rovided care is taken  
about where the lockdown procedure starts, it is normally possible for one TLB  
entry to cover all of  
these, in which case the first instruction prefetch after the TLB is invalidat  
ed can do this job.)  
If a data TLB is being locked down, ensure that all TLB entries are loaded whi  
ch relate to any data  
accessed by the rest of the lockdown procedure, including any inline literals   
used by its code. (This  
is usually best done by avoiding the use of inline literals in the lockdown pr  
ocedure and by putting  
all other data used by it in an area covered by a single TLB entry, then loadi  
ng one data item.)  
If a unified TLB is being locked down, do both of the above.  
5. For each of i = 0 to N-1:  
a. Write to register 10 with base == i, victim == i, and P == 1.  
b. Force a translation table walk to occur for the area of memory whose transl  
ation table walk  
result is to be locked into TLB entry i, by:  
• If a data TLB or unified TLB is being locked down, loading an item of   
data from the  
area of memory.  
• If an instruction TLB is being locked down, using the register 7 prefe  
tch instruction  
cache line operation defined in Register 7: Cache functions on page B5-15 to c  
ause an  
instruction to be prefetched from the area of memory.  
6. Write to register 10 with base == N, victim == N, and P == 0.