请教：关于Buck DC-DC

ddrr · 发表于 2009-2-27 08:44:59

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这种Clocked PFM，请问在active状态下，
是不是由于Io(输出电流)远小于IL（电感电流），因此无论时钟的占空比是多少，电荷在电容上的积累都将使Vout上升？

反过来，假设设计得不好，active状态下Io比较大，会不会按照一定的占空比（如50%）开关功率管，不能使Vout上升？

peacefeng · 发表于 2009-2-27 12:17:40

When it is in active mode, the circuit is openloop with a fixed duty cycle clock.
If DVdd > Vo, then whatever Io, inductor current will raise over Io and Vo could reach over target value eventually.

sillier · 发表于 2009-2-27 13:32:23

IL=Io/(1-D), D is duty clock, idea 50% duty clock, IL=2Io.
The is the max Io.

ddrr · 发表于 2009-2-27 16:15:44

应该还是和Io有关吧...simulink的结果:
轻载，拉高到14.4的情况可以看到IL>Io
而重载，IL＝Io

ddrr · 发表于 2009-2-27 19:22:49

waiting on line...

peacefeng · 发表于 2009-2-27 20:01:30

原帖由 ddrr 于 2009-2-27 16:15 发表

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应该还是和Io有关吧...simulink的结果:
轻载，拉高到14.4的情况可以看到IL>Io
而重载，IL＝Io

Vdd = 20V,Vref=15V, D=0.5.
When clk =0, diode is open or close?
If diode is close, the effective D > 0.5, otherwise D < 0.5.

peacefeng · 发表于 2009-2-27 20:19:45

原帖由 ddrr 于 2009-2-27 19:22 发表

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waiting on line...

建议楼主把Vo ripple and inductor current 的时域图贴上来。

我第一次的回复不太严谨。

我的想法是：

At steay state, taking a look with a long peirod, the effective duty cycle of converter should be D_eff = Vo/Vdd (when operate at CCM).

Thus the input clock duty cycle gives us the upper range of D_eff, or (D_eff)max = D_clk.

At light load, the coverter operates in DCM and D_eff is smaller than Vo/Vdd.

When load arises, D_eff is accordingly larger, the D_eff will be euqal to Vo/Vdd when the converter operates at CCM.
Once converter enters CCM, D_eff should not change in ideal case.
Practically D_eff needs to be larger than Vo/Vdd to compensate the parasitical loss.

Thus, the duty cycle of clock should be larger than Vref/Vdd when we use this topology.

As to your case, when load is light, the converter operates at DCM , therefore, you can get the Vo = 14.4.
While at heavy load, when converter operates at CCM, you can not get a Vo larger than Vdd*D_clk.