发几篇2008年最新的国外硕博士学位论文

fenglingke

A closed-loop Deep Brain Stimulation device with a logarithmic pipeline ADC
by Lee, Jongwoo, Ph.D., University of Michigan, 2008, 138 pages; AAT 3328877
Abstract (Summary)
     This dissertation is a summary of the research on integrated closed-loop deep brain stimulation for treatment of Parkinson's disease. Parkinson's disease is a progressive disorder of the central nervous system affecting more than three million people in the United States. Deep Brain Stimulation (DBS) is one of the most effective treatments of Parkinson symptoms. DBS excites the Subthalamic Nucleus (STN) with a high frequency electrical signal. The proposed device is a single-chip closed-loop DBS system. Closed-loop feedback of sensed neural activity promises better control and optimization of stimulation parameters than with open-loop devices.
     Thanks to a novel architecture, the prototype system incorporates more functionality yet consumes less power and area compared to other systems. Eight front-end low-noise neural amplifiers (LNAs) are multiplexed to a single high-dynamic-range logarithmic, pipeline analog-to-digital converter (ADC). To save area and power consumption, a high dynamic-range log ADC is used, making analog automatic gain control unnecessary. The redundant 1.5b architecture relaxes the requirements for the comparator accuracy and comparator reference voltage accuracy. Instead of an analog filter, an on-chip digital filter separates the low frequency neural field potential signal from the neural spike energy. An on-chip controller generates stimulation patterns to control the 64 on-chip current-steering DACs. The 64 DACs are formed as a cascade of a single shared 2-bit coarse current DAC and 64 individual bi-directional 4-bit fine DACs. The coarse/fine configuration saves die area since the MSB devices tend to be large.
     A prototype device is fabricated in 0.18 μm CMOS with a MiM capacitor option and occupies 2.67 mm 2 . The total power consumption of the entire system, including neural amplifiers, log ADC, current DAC, controller and digital filters, reference generation, clock generation and biasing, is 112 μW in normal operation mode and 351 μW in configuration mode, which is significantly less than that of state-of-the-art stimulator circuits.
    Real-time neural activity was recorded with the prototype device connected to microprobes that are chronically implanted in two Long Evans rats. The recorded in-vivo signal clearly shows neural spikes of 10.2 dB signal-to-noise ratio (SNR) as well as a periodic artifact from neural stimulation. The recorded neural information has been analyzed with single unit sorting and principal component analysis (PCA). The PCA scattering plots from multi-layers of cortex represent diverse information from either single or multiple neural sources. This exploits the benefits of a three-dimensional multi-layer neural probe such as Michigan probe. The single-unit neural sorting analysis along with PCA verifies the feasibility of the implantable CDBS device as an application to in-vivo neural recording interface. To program an optimal closed-loop algorithm, further intensive studies will be necessary to examine the neural pattern changes related to the CDBS treatment. In addition, the CDBS device and implantable brain-machine interface (BMI) unit, has potential for the treatment of other neurological disorders such as stroke, epilepsy and seizure.

fenglingke

A 1V 2.5GSs 8-bit self-calibrated flash ADC in 90nm GP CMOS
by Yu, Hairong, Ph.D., University of California, Los Angeles, 2008, 167 pages; AAT 3322043
Abstract (Summary)
    High-speed (GS/s), medium-resolution (6∼8b) and low-power analog-to-digital converters (ADCs) are essential in realizing multi-Gb/s communication systems. Ever increased devices mismatch, decreased supply voltage and excessive power consumption prevent current GS/s single-channel CMOS converters from being extended to 8-bit. The purpose of this research project is to develop a more efficient architecture to push the performance limit of high-speed medium-resolution converters, and to evolve the circuits necessary for implementing this architecture in deep-scaled digital CMOS technologies.
     Flash- and Folding-ADCs are the primary candidates for GS/s applications due to their high conversion speed and low latency. Though folding-ADCs use fewer comparators and simpler encoder circuits, they demand larger voltage headroom, are more sensitive to device mismatch and less amenable to calibration due to the folding action. In deep-scaled CMOS technologies, comparators and encoder circuits consume less power and silicon area, and therefore, flash ADCs can be pushed to achieve higher resolutions. This work presents an 8b flash ADC that employs THA buffer self-biasing and reference regeneration to boost the ADC full scale and correct mismatch induced offset errors without sacrificing the input bandwidth and sampling speed.
     The single-channel and two-channel interleaved prototype ADCs are fabricated in a 90nm GP CMOS. The single-channel ADC achieves 7, 6.9, 6.5 and 6.3 bit ENOB at 1.25GS/s for signal frequencies of 10MHz, 0.6, 1.3, and 1.95 GHz, respectively, and better than 50dB SFDR over 1.2GHz input band, while dissipating 243mW from a single 1V supply. The two-channel interleaved ADC attains 6.8, 6.5 and 6.0 bit ENOB at 2.5GS/s for signal frequencies of 10MHz, 300MHz and 1.1GHz, respectively, and consumes 453mW. The active die area for a single-channel and a two-channel ADC is 0.66mm 2 and 1.43mm 2 respectively.
      Compared with the state-of-the art of high-speed and medium-resolution converters, the single-channel ADC achieves the highest sampling rate of 1.55GS/s and widest effective resolution bandwidth of 1.3GHz, and cost-effective manufacturing.

fenglingke

A single-channel 10b 1GS/s ADC with 2-cycle latency using pipelined cascaded folding architecture
by Razzaghi, Alireza, Ph.D., University of California, Los Angeles, 2008, 255 pages; AAT 3316981
Abstract (Summary)
     Military surveillance, airborne early warning, and target recognition systems are swift decision making applications that require high-speed, low-latency electronics. These systems employ high dynamic range Digital Radar Receiver (DRR) that place the analog-to-digital converter (ADC) as close to the antenna as possible. This mandates the use of ADC architectures that achieve 10b of accuracy at GHz conversion rates with SFDR over 60 dB.
     The key features of this work are now summarized. An open-loop track-and-hold (THA) amplifier with enhanced linearity is designed to meet the wide dynamic range DDR specification. It maintains a linearity of 10.9b at low frequencies, with a negligible drop, to 10.5b at the Nyquist Frequency of 500MHz. Utilizing a single-channel quantizer and a highly linear front-end THA, the proposed ADC is not susceptible to the timing misalignments and limited linearity prevalent in CMOS time-interleaved architectures. The conversion speed of this ADC is improved by incorporating low-power distributed BiCMOS THAs after each folder. This significantly relieves the settling requirements by allowing each folder to settle within a dedicated clock cycle. An on-chip clock generator is designed to shift the phase of the master clock in eight steps, each 125ps, controlled by an off-chip three position switch. This is devised to ensure that, under random variations, pipeline stages sampling occurs after the dynamics of their inputs have subsided.
     A single-channel 10b 1GS/s ADC employing pipelined cascaded folding architecture is reported to achieve latency as low as 2 clock cycles for high dynamic range DRR applications. This ADC achieves a record 55.6dB peak SNDR and a 64dB peak SFDR. The DNL and INL at the sampling rate of 1GS/s are measured < 0.4LSB and 1.1LSB, respectively. Implemented in a 0.35&micro;m SiGe BiCMOS technology, the designed converter consumes 2W of power and occupies an active area of 4.5×1.2mm

getthegame

Thanks a lot.

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彭盛輝

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