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发表于 2009-2-19 04:47:16
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Physical Compiler, a key component of Synopsys’ Physical Synthesis solution, enables register-transfer level (RTL) designers to deliver the highest-performance circuits in the shortest time. By unifying synthesis and placement, Physical Compiler offers designers predictable timing closure - from RTL to placed-gates - for their most complex designs. Its proven interfaces to third-party routers allow it to easily plug into an existing design flow. Built upon the industry-standard Design Compiler™, Physical Compiler works seamlessly with Synopsys’ power, datapath, test and DesignWare® solutions. Physical Compiler is being widely adopted by the design community with multiple tapeouts attributed to it. Physical Compiler is enabling customers’ to meet their time to market requirements with significant performance and productivity gains. Leading ASIC vendors have also announced design kit support for Physical Compiler and are using placement handoff to quickly close on designs. |
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