FPGA在软件无线电（SDR）技术中越来越重要的作用

haichao

Wireless standards continue to evolve: adaptive modulation and coding, space-time coding and beam forming are, for example, designed to help satisfy the need for higher data rates. The events of 9/11 demonstrated the compelling need for communications systems interoperability and compatibility.
It’s no surprise, then, that software defines radio is capturing so much attention. Because traditional radio implementations are hardwired, they lack flexibility and ease of use – in effect, requiring a complete system redesign each time a new radio application challenge has to be met. Software defined radio (SDR) thus represents a complete paradigm shift: it replaces fixed, application-specific hardware with flexible, reconfigurable hardware that can be reprogrammed in order to deliver the required functionality, thus offering a degree of capability and flexibility that were previously not achievable. Software defined radio also represents a paradigm shift in that it moves radio applications from the Analog domain to a domain where the majority of functions are implemented digitally.
The availability of very high speed digital to analog converters (DAC) for transmit and analog to digital converters (ADC) for receive have, to a large extent, made the SDR revolution possible – as has the availability of successive generations of dsp technology which move very high speed digital data between these converters and process it in real time.
Digital signal processing has traditionally been at the heart of software defined radio, and the function can be accomplished using a range of hardware solutions: application specific integrated circuits (asic); purpose-designed digital signal processors; and general purpose processors.
But now, another shift in technology is taking place which is transforming the market for software defined radio just as it is transforming other markets. The technology in question is FPGA (field programmable gate array). Rapid advances in the gate capacity and operating speed of FPGAs has opened up an opportunity for performing real-time digital signal processing on a single FPGA that was not possible several years ago, making it suitable for applications that demand not only the high speed, compute-intensive performance currently delivered by digital signal processing, but also reconfigurability. Reconfigurable cores are now available from a range of vendors that enable the implementation of modulator, demodulator and CODEC functionality in the FPGA.
Beyond this, new FPGA devices utilize extremely small silicon geometries that allow very high clock speeds at low core voltages, while Ball Grid Array (BGA) packaging enables the provision of thousands of I/O lines from a compact footprint.
FPGA technology is thus becoming an increasingly important player in software defined radio primarily because of the additional flexibility it brings – and flexibility is the defining characteristic of the new approach to radio applications. FPGAs have evolved from being a flexible logic design platform to a signal processing engine: not only are system designers porting an increasing number of signal processing functions in FPGAs, but also the flexibility of having the ability to integrate logic design with signal processing is driving designers to replace traditional DSPs with FPGAs.
FPGAs are inherently suited for computationally-intensive, applications such as very high-speed parallel multiply and accumulate functions. Current generation FPGAs can perform 18 x 18 multiplication operation at speeds in excess of 200 MHz. This makes FPGAs an ideal platform for operations such as FFT (Fast Fourier Transform), FIR (???), Digital Down Converters (DDC), Digital Up Converters (DUC), correlators, pulse compression (for radar processing) and so on. It does not imply, however, that all DSP functionalities may be implemented in FPGAs. Floating point operations are extremely difficult to implement in FPGAs due to the large amount of real estate needed in the device. Also, processing involving matrix inversion (or division) is also more suited in a DSP/GPP platform. FPGAs and DSP will thus co-exist for a long time.
FPGA design is inherently a hardware design effort and not simply a DSP coding exercise. Progress in the field of EDA (electronic design automation) tools has ensured that better and more accurate design and simulation software is in the market. The FPGA vendors, such as Xilinx and Altera, have also been instrumental in driving tool development, thereby improving the ease of FPGA design. The hardware nature of FPGA design, however, can lead to unplanned project delays as the right engineering resources are not budgeted for the task. The process which is designed to deliver functional hardware with the integrated functionality from a pre-packaged FPGA IP (intellectual property) core is one that needs to be planned carefully.
It is possible to obtain complete many of the functional structures required by software defined radio in the form of intellectual property (IP) cores ‘off the shelf’ from FPGA vendors and a growing number of third party companies. Many of these parameter-driven cores allow the system designer significant flexibility – allowing a trade off to be made, for example, between FPGA capacity and accuracy.
Integration of these cores in COTS modules, however, still needs to be achieved, and this has led to a rise in the availability of so-called ‘integrated cores’ – the provision, for example, of baseband FPGA functionalities with high performance data acquisition subsystems to provide a complete, smart front end system. These can be provided with application examples that are designed to reduce system design times and integration risks – enabling solutions to be developed that are more cost-effective and quicker to market.
An example of such an approach might be the application for beamforming for phased array radar. Phased array radars with large number of elements are becoming extremely common for next generation radar systems. These systems handle high bandwidth and thus pass a large amount of data back and forth, and the challenge is to build a synchronized system with synchronization between multiple DDCs and high-speed data transfer between modules.
To enable a solution to be developed in the shortest time and at the lowest cost, ICS developed and delivered a prototype system that implements a 2x2 beamformer at 40 and 20 MHz bandwidths. Two ICS-554 105 MHz/channel (maximum sampling frequency) analog input boards are used to acquire four analog channels. For the 20 MHz bandwidth case, each ICS-554 generates four partial beams, of which two are sent to the other ICS-554. Each ICS-554 generates two full beams by combining two partial beams generated internally with two partial beams received from the other ICS- 554. The data transfer between boards is 200 MBytes/sec in each direction for a total of 400 MBytes/sec over LVTTL (low volate transistor-to-transistor logic). It is expected that implementing an LVDS interface will dramatically increase data transfer, leading to increased bandwidth. Larger beamforming may be very easily implemented on the ICS-572 platform which offers a much larger FPGA (up to eight million gates) and large on-board memory.
The concept of the FPGA has been around since the early 1980s, and it is probably true to say that early generations of FPGA technology acted mostly as the ‘glue logic’ for systems. Today’s FPGAs, though, with their vastly increased capabilities, are capable of an enormous variety of sophisticated applications – emulating a single, traditional processor representing the simplest of those, and containing a complete, custom system-on-a-chip representing perhaps the most advanced.
Capable of dynamic reconfiguration, and delivering exceptional performance, FPGA technology has both the flexibility and the power needed for software defined radio to continue the rapid progress it has made in recent years. That FPGAs will supersede DSPs, ASICs and general purpose processors in the field of SDR seems unlikely: a more likely scenario is that they will happily co-exist, but with FPGAs assuming increasing importance.

dusy

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