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作者包括好几个IEEE Fellow，包括大牛Wooley，本文原载于JSSC 2008 -Issue 10
Abstract—This paper presents a CMOS RF power amplifier that
employs a digital polar architecture to improve the overall power
efficiency when amplifying signals with high linearity requirements.
The power amplifier comprises 64 parallel RF amplifiers
that are driven by a constant envelope RF phase-modulated signal.
The unit amplifiers are digitally activated by a 6-bit envelope
code to construct a non-constant envelope RF output, thereby
performing a digital-to-RF conversion. In order to suppress the
spectral images resulting from the discrete-time to continuous-time
conversion of the envelope, the use of oversampling and four-fold
linear interpolation is explored. An experimental prototype of
the polar amplifier has been integrated in a 0.18- m CMOS
technology, occupies a total die area of 1.8 mm2, operates at a
1.6-GHz carrier frequency with a channel bandwidth of 20 MHz.
For an OFDM signal, it achieves a power-added efficiency of 6.7%
with an EVM of 26.8 dB while delivering 13.6 dBm of linear
output power and drawing 145 mA from a 1.7-V supply.
Index Terms—CMOS RF, IEEE 802.11g, L-fold linear interpolation,
polar transmitter, power amplifier.
A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth.pdf
(1.41 MB, 下载次数: 397 )
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发表于 2009-2-13 22:31:02
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