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发表于 2009-2-10 17:25:27
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21 Design and Optimization of an HSDPA Turbo Decoder ASIC
Abstract—The turbo decoder is the most challenging component
in a digital HSDPA receiver in terms of computation requirement
and power consumption, where large block size and recursive algorithm
prevent pipelining or parallelism to be effectively deployed.
This paper addresses the complexity and power consumption
issues at algorithmic, arithmetic and gate levels of ASIC design, in
order to bring power consumption and die area of turbo decoders
to a level commensurate with wireless application. Realized in
0.13 m CMOS technology, the turbo decoder ASIC measures
1.2 mm2 excluding pads, and can achieve 10.8 Mb/s throughput
while consuming only 32 mW.
Design and Optimization of an HSDPA Turbo Decoder ASIC.pdf
(1.19 MB, 下载次数: 90 )
22 Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance
Abstract—A 65 nm resilient circuit test-chip is implemented
with timing-error detection and recovery circuits to eliminate the
clock frequency guardband from dynamic supply voltage 􀀀􀀀􀀀
and temperature variations as well as to exploit path-activation
probabilities for maximizing throughput. Two error-detection sequential
(EDS) circuits are introduced to preserve the timing-error
detection capability of previous EDS designs while lowering clock
energy and removing datapath metastability. One EDS circuit is a
dynamic transition detector with a time-borrowing datapath latch
(TDTB). The other EDS circuit is a double-sampling static design
with a time-borrowing datapath latch (DSTB). In comparison to
previous EDS designs, TDTB and DSTB redirect the highly complex
metastability problem from both the datapath and error path
to only the error path, enabling a drastic simplification in managing
metastability. From a survey of various EDS circuit options,
TDTB represents the lowest clock energy EDS circuit known;
DSTB represents the lowest clock energy static-EDS circuit with
SER protection known. Error-recovery circuits are introduced to
replay failing instructions at lower clock frequency to guarantee
correct functionality. Relative to conventional circuits, test-chip
measurements demonstrate that resilient circuits enable either
25%–32% throughput gain at equal 􀀀􀀀 or at least 17% 􀀀􀀀
reduction at equal throughput, corresponding to 31%–37% total
power reduction.
abbr_9af595bdc007def6cc126e703a72a074.pdf
(1.77 MB, 下载次数: 73 )
23 High Dynamic Range CMOS Imager Technologies for Biomedical Applications
Abstract—Apart from the ongoing debate about usingCMOSactive
pixel sensors (APS) or CCD imagers for today’s consumer and
commercial applications the emerging biomedical market presents
new opportunities to CMOS APS. Logarithmic response High-Dynamic
RangeCMOS(HDRC) cells are the preferred photosensitive
circuits for building sensors with contrast and not with illumination
dominated outputs. Prominent examples addressing distinct
issues in life style and health care are the possibilities to restore vision
through a sub-retinal CMOS imager implant and to fabricate
a low-cost intracorporeal video probe through a miniature CMOS
imager. The sub-retinal imager chip presented here is the first implanted
into the eye of a blind human patient with partial restoring
of vision.
High Dynamic Range CMOS Imager Technologies for Biomedical Applications.pdf
(2.6 MB, 下载次数: 92 )
24 iVisual- An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS per W Vision Processor
Abstract—Apart from the ongoing debate about usingCMOSactive
pixel sensors (APS) or CCD imagers for today’s consumer and
commercial applications the emerging biomedical market presents
new opportunities to CMOS APS. Logarithmic response High-Dynamic
RangeCMOS(HDRC) cells are the preferred photosensitive
circuits for building sensors with contrast and not with illumination
dominated outputs. Prominent examples addressing distinct
issues in life style and health care are the possibilities to restore vision
through a sub-retinal CMOS imager implant and to fabricate
a low-cost intracorporeal video probe through a miniature CMOS
imager. The sub-retinal imager chip presented here is the first implanted
into the eye of a blind human patient with partial restoring
of vision.
abbr_1735947a32d94d1f30e31138e5b9d064.pdf
(1.89 MB, 下载次数: 77 )
25 Low-Power 16 x 10 Gb per s Bi-Directional Single Chip CMOS Optical Transceivers Operating at smaller than 5 mW per Gb per s per link
Abstract—We report here on a parallel optical transceiver based
on a single 0.13 m CMOS amplifier chip with 16 transmitter
and 16 receiver channels. The transceiver is designed to support
very low-power, chip-to-chip optical data buses on printed circuit
boards at data rates up to 10 Gb/s/channel. Optical interfaces to
the chip are provided by 16-channel photodiode (PD) and VCSEL
arrays directly flip-chip soldered to the CMOS IC. The resulting
complete transceivers, or Optochips, are low-cost, low-profile
highly-integrated chip-scale components. The packaging approach,
dense hybrid-integration of optical devices with CMOS,
facilitates further scaling to even larger 2-D arrays for future massively
parallel optical data buses. Comparison with a previously
reported high-speed transceiver Optochip is provided to provide
insight into the design space of dense CMOS-based parallel optical
transceivers.
All of the Optochip transmitter and receiver channels operate at
10 Gb/s for an aggregate bi-directional data rate of 160 Gb/s. Direct
measurements of inter-channel crosstalk at 10 Gb/s indicate negligible
power penalties. The transceiver measures 3.25 5.25 mm
and consumes 708mWof power with all channels fully operational.
The area efficiency achieved by the Optochip is 9.4 Gb/s/mm􀀀 per
link, and the per-bit power consumption of 4.44 mW/Gb/s is unprecedented
for parallel optical modules.
abbr_16d73490897215edbd92024fe3b97f23.pdf
(2.7 MB, 下载次数: 81 )
26 RazorII- In Situ Error Detection and Correction for PVT and SER Tolerance
Abstract—Traditional adaptive methods that compensate for
PVT variations need safety margins and cannot respond to
rapid environmental changes. In this paper, we present a design
(RazorII) which implements a flip-flop with in situ detection
and architectural correction of variation-induced delay errors.
Error detection is based on flagging spurious transitions in the
state-holding latch node. The RazorII flip-flop naturally detects
logic and register SER. We implement a 64-bit processor in
0.13 m technology which uses RazorII for SER tolerance and
dynamic supply adaptation. RazorII based DVS allows elimination
of safety margins and operation at the point of first failure
of the processor. We tested and measured 32 different dies and
obtained 33% energy savings over traditional DVS using RazorII
for supply voltage control. We demonstrate SER tolerance on the
RazorII processor through radiation experiments.
RazorII- In Situ Error Detection and Correction for PVT and SER Tolerance.pdf
(2.59 MB, 下载次数: 97 )
27 Ultra-Sensitive Capacitive Detection Based on SGMOSFET Compatible With Front-End CMOS Process
Abstract—Capacitive measurement of very small displacement
of nano-electro-mechanical systems (NEMS) presents some issues
that are discussed in this article. It is shown that performance is
fairly improved when integrating on a same die the NEMS and
CMOS electronics. As an initial step toward full integration, an
in-plane suspended gate MOSFET (SGMOSFET) compatible with
a front-end CMOS has been developed. The device model, its fabrication,
and its experimental measurement are presented. Performance
obtained with this device is experimentally compared to the
one obtained with a stand-alone NEMS readout circuit, which is
used as a reference detection system. The 130nmCMOSASIC uses
a bridge measurement technique and a high sensitive first stage to
minimize the influence of any parasitic capacitances.
abbr_24ce6db8176a709fdb9a46a83189b87b.pdf
(3.68 MB, 下载次数: 94 )
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发表于 2009-2-10 16:17:15
