thesis about continuous high speed sigma delta design

adanshen

here is a good thesis about wide-band sigma delta data converter design.

Design of a 14-bit Continuous-Time Delta-Sigma A/D Modulator

with 2.5MHz Signal Bandwidth

In recent years, there has been growing interest in both industry and

academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless

and wireline communication applications.

So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher

dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s).

This dissertation presents the realization of a continuous-time (CT) Δ-Σ A/D

modulator providing 80.5dB SNDR and 85dB DR with 5MS/s output data rate in a

2.5V 0.25μm CMOS process. The modulator has a single-stage dual-loop

architecture allowing large quantizer delay. A 17-level quantizer is used to increase

resolution and non-return-to-zero DACs are adopted to reduce clock jitter

sensitivity. Capacitor tuning is utilized to overcome time-constant variation. Onchip

self-calibration is implemented to suppress DAC nonlinearity. Combining

techniques to address various design challenges, the modulator consumes 50mW

with 60MHz sampling rate.

another basic one:

Continuous-Time Delta-Sigma A/D Converters for

High Speed Applications


[ 本帖最后由 adanshen 于 2009-1-14 03:01 编辑 ]

liuzhieetop

:victory: :victory:

ccmayo

xiexie

termi

非常好!

两篇都是对CT SDM design很有用的thesis,比paper要详细多了!!!

谢谢LZ

smartboy918

thanks

rachel0131

:victory:

joojli1

moorehuang

好东西，顶一个

leonken460

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leonken460

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