求助：如何让数字寄存器的状态不被ESD打翻

syncom · 发表于 2009-12-24 18:23:45

會不會進入metastable,然後又因為沒有clock持續的進入,造成不正常的準位持續送出.
register如果有clock一直進入的話,應該不會是在中間電平.....

lhtlht888 · 发表于 2009-12-30 14:31:01

good......

g9213706 · 发表于 2009-12-31 01:27:02

10# andyjackcao
I think ESD and logic are indepand design.
do yu have check all the setup time and hold time are meet your design.
it may cause multistable to let function.

求助：如何让数字寄存器的状态不被ESD打翻

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