打开design analyzer后，当我read一个VHDL/verilog文件时就会出错退出
error：id=445313
the tool has just encountered a fatal error:
If you encountered this fatal error when using the most recent Synopsys releas,submit this stack trace and a test case that reproduces the problem to the synopsys support
Ftal: Internal system error, can not recover
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2008-12-8 11:51:22
。。。。比GUI好。