IEEE 系列论文

flyfeng

SOI：

• Ching-Te Chuang, Pong-Fei Lu, and Carl J. Anderson, "SOI For Digital CMOS VLSI: Design Considerations and Advances," Proceedings of the IEEE, April, 1998, pp. 689 - 720
• A. G. Aipperspach, D. H. Allen, D. T. Cox, H. V. Phan, and S. N. Storino, "A 0.2-um, 1.8-V, SOI, 500-MHZ, 64-b PowerPC microprocessor with copper interconnects," IEEE Journal of Solid-State Circuits,  November, 1999, pp. 1430-1435.
• K. L. Shepard and D.-J. Kim, "Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis," IEEE Transactions on Computer-Aided Design on Integrated Circuits and Systems, July, 2001, pp. 888-901.

flyfeng

PLL/DLL ：
Design John G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits, November, 1996, pp. 1723 - 1732.
P. Larsson, "High-speed architecture for a programmable frequency divider and a dual-modulus prescalar," IEEE Journal of Solid-State Circuits, November, 1996, pp. 744-748.
Stefanos Sidiropoulos, Dean Liu, Jeaha Kim, Guyeon Wei, and Mark Horowitz, "Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers, Symposium on VLSI Circuit Digest of Technical Papers, 2000, pp. 124-127.
Stefanos Sidiropoulous and M. A. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE Journal of Solid-State Circuits, November, 1997, pp. 1683-1692.

dtao

好................ :) :) :) :) :) :)

hujiaomianhao

ddddddddddddddddddd

flyfeng

Advanced CMOS Technology Issues

• S. Borkar, "Design challenges of technology scaling," IEEE Micro, July-August, 1999, pp. 23-29.
• B. Davari et al., "CMOS scaling for high performance and low power - the next ten years," Proceedings of the IEEE, April, 1995.

zhanweisu27

很好

高级芯片一万年也要搞出来

superlazer

强烈支持楼住~~~~~~~