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发表于 2010-1-8 05:54:03
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Phase-locked loops (PLL) are at the core of some important RF designs such as frequency synthesis, clock and data recovery, and clock de-skew. Some of the PLL characteristics, such as phase noise, jitter, power supply and substrate noise interference, step response, acquisition time, and static phase offset are of interest to most designers, but to measure these characteristics, the simulator must overcome the following obstacles:
The large difference in the time-constant between the VCO and other PLL blocks
The VCO can operate in the range of GHz; the PFD and CP in the range of MHz; the output of LPF and control of VCO in the range of KHz. Transient analysis forces all the PLL blocks to use the same small time-steps required by the VCO frequency, which makes the analysis very time-consuming.
The VCO is an autonomous circuit while the other blocks are driven circuits
PSS and QPSS analyses cannot simulate this kind of circuit.
The PLL generates repetitive switching events as an essential part of its operation, and the noise performance must be evaluated in the presence of this large-signal behavior
Transient noise analysis is very time-consuming and neither PNOISE nor QPNOISE analyses can be used.
The Spectre RF noise-aware PLL flow provides a solution to these challenges. This flow uses a macro-model based simulation methodology, in which the PFD-CP, VCO, and divider in the PLL are replaced by automatically generated macro-models that characterize the behavior of the original blocks. The VCO and the divider are integrated into one macro-model, greatly improving the simulation efficiency. In addition, both integer N and fractional-N PLLs can be simulated. |
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