Sorry I can't key in Simplified Chinese
You may refer to TSMC reference flows, that is most advanced ASIC design flow
Be able to handle
10+ millions instances SOC designs
hierarchical planning and analysis
DFT knowledge and deal with boundary scan, core test, memory bist, compression scan chains
DFM knowledge and deal with metal density, dummy metal fill, virtual CMP to timing, lithography & routing
handles Low Power , power off, voltage frequency scheduling with multi-corner, multi-mode
handles Signal integrity, crosstalk & electron migration issues
handles power spec. to floorplan, i.e. voltage drop, power noise, SSO, decoupling cap, well tap etc.
handles on-chip variations, with gated clocks, and state-retantion filpflops
handles special circuits, such as analog, high frequency or RF, DDR, differential pair signal
If you are good at above topics, you may start to implement TCL or C (with APIs) to deal your own back-end problems, refer to most CAD labs research topics in the university. |
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发表于 2008-11-6 09:21:43
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