//Next state logic
always @ (ads_b or blast_b or Pci_Csta) //rdy_b or or lclk
begin
Pci_Nsta=Pci_Csta;
case (Pci_Csta)
s0_idle: if (!ads_b)
Pci_Nsta = s1_start;
else
Pci_Nsta = s0_idle;
s1_start: if (!blast_b)
Pci_Nsta = s2_single_wait;
else if (blast_b)
Pci_Nsta = s4_burst_wait;
else
Pci_Nsta = s1_start;
s2_single_wait:
Pci_Nsta = s3_single_last;
s3_single_last: if (!ads_b)
Pci_Nsta = s1_start;
else
Pci_Nsta = s0_idle;
s4_burst_wait: Pci_Nsta = s5_burst_repeat;
s5_burst_repeat: if (blast_b)
Pci_Nsta = s5_burst_repeat;
else
Pci_Nsta = s6_burst_last;
s6_burst_last: if (!ads_b)
Pci_Nsta = s1_start;
else
Pci_Nsta = s0_idle;
default:
Pci_Nsta = s0_idle;
endcase
end
//output logic
always @ (posedge lclk)
begin
lrdy<=1'b1;
case(Pci_Nsta)
s0_idle: begin
lrdy <=1;
// watch_sta<=3'b000;
end
s1_start: begin
lrdy <=1;
// watch_sta<=3'b001;
end
s2_single_wait: begin
lrdy<=0;//2008/07/04 15:33
// watch_sta<=3'b010;
end
s3_single_last: begin
lrdy<=1;
// watch_sta<=3'b011;
end
s4_burst_wait: begin
lrdy<=1;
// watch_sta<=3'b100;
end
s5_burst_repeat: begin
lrdy<=0;
// watch_sta<=3'b101;
end
s6_burst_last: begin
lrdy<=1;
// watch_sta<=3'b110;
end
default: begin
lrdy<=1;
// watch_sta<=3'b110;
end
endcase
end
//------------------------------------------------
// local bus arbitration
always @(posedge lclk)
if (lhold)
lholda <= lhold;
else
lholda <= 1'b0;